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handshake solutions HT80C51 user manual document information page 2 of 132 ? philips electronics n.v. 2005 document information document title HT80C51 user manual date of creation 27/06/2005 date of last change 27/06/2005 file name HT80C51-usermanual.doc status release version number 1.7 client / target audience system architec ts,and software developers using the HT80C51 summary this document describes and illustrates the general architecture, the standard peripherals and the inst ruction set for the HT80C51. contact handshake solutions high tech campus prof. holstlaan 4 mailbox wam01 5656 aa eindhoven the netherlands phone: +31-40-27 46114 fax: +31-40-27 46526 info@handshakesolutions.com www.handshakesolutions.com ? 2005 koninklijke philips electronics n.v. all rights reserved. reproduction in whole or in part in any way, shape or form, is prohibited without the written consent of the copyright owner. all information in this document is subject to change with- out notice.
HT80C51 user manual table of contents handshake solutions ? philips electronics n.v. 2005 page 3 of 132 table of contents 1. introduction to HT80C51 ........................................................................................................ ....... 5 1.1. compatibility .................................................................................................................. ... 5 1.2. modules........................................................................................................................ ...... 6 2. memory orga nization ............................................................................................................ ........ 9 2.1. memory map ..................................................................................................................... .9 2.2. accessing program memory ......................................................................................... 10 2.3. accessing external data memory ................................................................................. 10 2.4. internal data memory: direct and indirect a ddress ar ea........................................... 11 2.5. special function registers............................................................................................ 13 2.5.1. accumulato r acc .............................................................................................. 14 2.5.2. register b .......................................................................................................... 14 2.5.3. program status word psw............................................................................... 14 2.5.4. stack pointer sp ............................................................................................... 14 2.5.5. data pointer dp tr dph dpl ........................................................................... 15 2.5.6. power saving m odes pcon ............................................................................. 15 2.5.7. external ram page xramp ( option HT80C51_cp u_xramp)....................... 17 2.6. movc protection (option HT80C51_cpu_ movcp)..................................................... 17 3. reset .......................................................................................................................... ................... 18 4. clocks ......................................................................................................................... .................. 19 4.1. cpu co ck....................................................................................................................... .. 19 4.1.1. clockless (aynchrono us) cnfiguration .............................................................. 19 4.1.2. clock synchronization (opt ion HT80C51_c pu_sync) ................................... 19 4.2. peripheral clocks ............................................................................................................ 19 5. peripheral modules............................................................................................................. ......... 20 5.1. interrupt co ntrolle r ......................................................................................................... 20 5.1.1. options .............................................................................................................. 20 5.1.2. special function registers (ien0 ien1 ip0 ip1) ................................................. 20 5.1.3. operatio n ........................................................................................................... 22 5.1.4. setting up the interru pt contro ller ..................................................................... 25 5.2. timers 0 and 1 ................................................................................................................. 26 5.2.1. options .............................................................................................................. 26 5.2.2. special function registers (tmo d tcon tl0 tl1 th0 th1)........................... 26 5.2.3. interrupt s............................................................................................................ 28 5.2.4. operatio n ........................................................................................................... 29 5.2.5. setting up the timers ........................................................................................ 31 5.3. standard serial in terface (s io0) .................................................................................... 33 5.3.1. options .............................................................................................................. 33 5.3.2. special function register s (scon sbuf smod) .............................................. 33
handshake solutions HT80C51 user manual table of contents page 4 of 132 ? philips electronics n.v. 2005 5.3.3. interrupt s............................................................................................................ 34 5.3.4. operatio n ........................................................................................................... 34 5.3.5. setting up the se rial port.................................................................................... 40 5.4. general pur pose io s ...................................................................................................... 42 5.4.1. options .............................................................................................................. 42 5.4.2. special function regist ers (poutx pinx) .......................................................... 42 5.4.3. interrupt s............................................................................................................ 43 5.4.4. operatio n ........................................................................................................... 43 5.5. i 2 c interface (sio1) .......................................................................................................... 44 5.5.1. options .............................................................................................................. 44 5.5.2. special function registers (s1c on s1adr s1da t s1sta ) ........................... 44 5.5.3. interrupt s............................................................................................................ 46 5.5.4. operatio n ........................................................................................................... 46 5.5.5. slave-only ve rsion ............................................................................................. 73 5.5.6. application notes ............................................................................................... 73 5.6. serial peripheral in terface ( spi) .................................................................................... 74 5.6.1. options .............................................................................................................. 74 5.6.2. special function regist ers (spcr spsr spdr) ............................................... 74 5.6.3. interrupt s............................................................................................................ 76 5.6.4. operatio n ........................................................................................................... 76 5.7. watchdog timer (unde r developm ent) ......................................................................... 80 5.7.1. options .............................................................................................................. 80 5.7.2. special function r egisters (t3)........................................................................... 80 5.7.3. interrupt s............................................................................................................ 80 5.7.4. operatio n ........................................................................................................... 80 5.8. triple-des c onverte r...................................................................................................... 82 5.8.1. options .............................................................................................................. 82 5.8.2. special function register s (dcon dkey dtxt) ............................................... 82 5.8.3. interrupt s............................................................................................................ 83 5.8.4. operatio n ........................................................................................................... 83 5.8.5. software view .................................................................................................... 84 6. 80c51 family inst ruction set................................................................................................... ... 87 6.1. 80c51 instruction set summary.................................................................................... 87 6.2. instruction de finitions .................................................................................................... 91 appendix ....................................................................................................................... ..................... 130 a1: list of tables ................................................................................................................. 130 a2: list of figures ............................................................................................................... 1 31 a3: document hi story ......................................................................................................... 132
HT80C51 user manual introduction to HT80C51 ? compatibility handshake solutions ? philips electronics n.v. 2005 page 5 of 132 1. introduction to HT80C51 the handshake technology 80c51 (referred to as ht 80c51) is an improved version of the ultra low- power 80c51 (known as ulp80c51). this ulp80c51 has been used in several products such as pagers, game controllers, telephony controllers, and mifare prox and smartmx smart card controllers. millions of these ics have been shipped. the HT80C51 implementation offers several unique features, which are detailed below. ? the HT80C51 is extremely low power (the cpu consumes only 0.1 nano joules per instruction). ? the HT80C51 has very low electromagnetic emission (eme). ? the HT80C51 has low supply-current peaks (at least a factor five lower than traditional, clocked implementations), thus facilitating int egration with analog and rf circuitry. ? the HT80C51 cpu consumes zero stand-by power while in sleep mode, yet is immediately available for full-speed full-functional operation. ? the HT80C51 has an asynchronous and optiona lly a synchronous mo de of operation. when both are present, the actual mode can be dynamically selected on an instruction-per-instruction base. this is controlled via a dedicated input. ? in asynchronous mode of operation, the cpu runs at it s natural speed, and a slow core clock does not slow it down. ? in synchronous mode, the cpu synchronizes with a clo ck on a machine cycle basis after each instruction in such a way that the number of clock cycles for that instruction is the same as the number of machine cycles for a synchronous implementation. ? the HT80C51 core is configurable, and has a r ange of configuration options, offering selective instantiations of 80c51 peripherals and customization of memory interfaces. ? the HT80C51 peripherals consume zero power when not actively used. ? optional dual datapointer (for more compact code). ? optional movc protection (only grants progra m code from lower program memory permission to read lower program memory). 1.1. compatibility the HT80C51 implementation is functionally compatible to the instruction set and the peripherals of the original 80c51. the HT80C51 and its peripherals have been designed in haste, which is the high-level programming language of the handshake technology design flow. th is design flow is to a large extent technology independent. mapping onto various vlsi technologies from different vendors is supported. for production testing, both functional and scan-test version are supported. the scan-test version is compatible with standard atpg tools.
handshake solutions HT80C51 user manual introduction to HT80C51 ? modules page 6 of 132 ? philips electronics n.v. 2005 1.2. modules following modules are currently availabl e for a HT80C51 microcontroller system ? HT80C51 cpu with optional - prefetch unit to increase performance - dual datapointer - movc protection - synchronization to external clock ? interrupt controller - with configurable number of interrupt lines (1 to 15) ? timer 0 and timer1 ? uart ? spi ? i2c - master/slave or - slave only ? watchdog timer ? des ? bridge to synchronous sfr bus - supports legacy synchronous peripheral units other peripherals are being developed or can be implemented on demand.
HT80C51 user manual introduction to HT80C51 ? modules handshake solutions ? philips electronics n.v. 2005 page 7 of 132 code address external data address xramp buffer register pc incrementer pc dptr dptr1 code memory external data memory instruction register control psw peripheral special function registers peripheral logic pcon external logic alu tmp2 tmp1 stack pointer b acc internal data address ram HT80C51 [figure 1] HT80C51 architecture (cpu centered)
handshake solutions HT80C51 user manual introduction to HT80C51 ? modules page 8 of 132 ? philips electronics n.v. 2005 up to 64kbytes external data memory (optional) up to 64kbytes program memory up to 256bytes internal data memory handshake peripherals synchronous peripherals synchronous sfr bus bridge 80c51 cpu gpio watchdog des spi i 2 c uart timer 0 / 1 interrupt controller int4,5,6 int_req_i[ ] int _ack_o[ ] int 0..3 gpio_pinx[ ] t1_overflow gpio_poutx[ ] external HT80C51 ht-sfr bus [figure 2] HT80C51 achitecture
HT80C51 user manual memory organization ? memory map handshake solutions ? philips electronics n.v. 2005 page 9 of 132 2. memory organization the 80c51 architecture comprises several different and separated address areas. the following chap- ter describes the map of these memory areas, which are described in more detail thereafter. 2.1. memory map the 80c51 has separate address spaces for program memory, external and internal data memory. [figure 3] shows a map of the 80c51 memory areas. up to 64 kbytes up to 64 kbytes up to 256 bytes internal data memory (idata, data) external data memory (xdata) program memory (code) 000h fffh ffh 00h [figure 3] HT80C51 memory map the program memory (code) can be up to 64kbytes. it can be accessed by instruction fetches and by the movc instruction. the 80c51 can address up to 64k by tes of external data memory (xdata ). historically this area was located outside the chip (hence the name external ), which is usually not the case for embedded sys- tems. the movx instruction is used to access the external data memory. the 80c51 can address up to 256 bytes of on-chip ra m, plus a number of special function registers (sfrs). the lower 128 bytes of ram can be accessed either by direct addressing (mov data addr) or by indi- rect addressing ( mov @ri ). the upper 128 bytes of ram can be accessed by indirect addressing only. using addresses 80h to ffh with direct addressing accesses the special function registers. [figure 4] shows the internal data memory organization.
handshake solutions HT80C51 user manual memory organization ? a ccessing program memory page 10 of 132 ? philips electronics n.v. 2005 special functions registers (sfrs) upper area of ram (128 bytes) lower area of ram (128 bytes) direct addressing (data) indirect addressing (idata) internal data memory ffh 80h 7fh 00h [figure 4] memory map of internal data 2.2. accessing program memory the program memory is readable only and can be accessed by two access methods: instruction fetches using the 16bit program counter (pc) as the address or move-code instructions using the 16bit data pointer ( movc @dptr ) or again the pc ( movc @pc ) as reference. 2.3. accessing external data memory in contrast to the program memory the external da ta memory is read- and writeable. accesses to ex- ternal data memory can be done thru the movx-inst ruction only, which comes in two flavors: movx @dptr uses the data pointer to form the 16bit address. movx @ri uses one of the index registers to form the lower 8bits of the address with the upper part of the address being defined by the sfr xramp . the first variant is usually faster and a more general access method. the second variant ( movx @ri ) can be used as a paging access to a rather small area of data.
HT80C51 user manual memory organization ? internal data memory: direct and indirect address area handshake solutions ? philips electronics n.v. 2005 page 11 of 132 2.4. internal data memory: dir ect and indirect address area the lower 128 bytes of ram can be accessed by bot h direct and indirect addressing and they can be divided into three segments as listed below and shown in [figure 5]. register bank 0 register bank 1 register bank 2 register bank 3 bit addresses 00 ? 7f scratch pad area bit addressable segment register banks 7fh 30h 2fh 20h 1fh 18h 17h 10h 0fh 08h 07h 00h [figure 5] lower 128 bytes of ram, direct and indirect addressing 1. register banks 0-3: locations 00h through 1fh (32 bytes). the device after reset defaults to register bank 0. to use the other register banks, the us er must select them in software. each register bank contains eight 1-byte registers 0 through 7. reset initializes the stack pointer to location 07h , and it is incremented once to start from location 08h , which is the first register ( r0 ) of the second register bank. thus, in order to use more than one register bank, the sp should be initialized to a different location of the ram where it is not used for data storage (i.e ., the higher part of the ram). the register bank is selected by bits rs0 and rs1 in the program status word. 2. bit addressable area: 16 bytes have been assigned for this segment, 20h-2fh . each one of the 128 bits of this segment can be directly addressed ( 0-7fh ). the bits can be referred to in two ways, both of which are accept-
handshake solutions HT80C51 user manual memory organization ? internal data memory: direct and indirect address area page 12 of 132 ? philips electronics n.v. 2005 able by most assemblers. one way is to refer to their address (i.e., 0-7fh ). the other way is with ref- erence to bytes 20h to 2fh . thus, bits 0-7 can also be referred to as bits 20.0-20.7 , and bits 8-fh are the same as 21.0-21.7 , and so on. each of the 16 bytes in this segment can also be addressed as a byte. 3. scratch pad area: 30h through 7fh are available to the user as data ram. ho wever, if the stack pointer has been initial- ized to this area, enough bytes should be left aside to prevent overwr iting of stack data.
HT80C51 user manual memory organization ? special function registers handshake solutions ? philips electronics n.v. 2005 page 13 of 132 2.5. special function registers the upper address range of the dire ct addressable data memory is oc cupied by the special function registers (sfrs). these registers not only serve as data storage, they also have special function for the cpu or peripherals they are attached to. a map of this area is shown in [figure 6]. f8 ff f0 b spcr spsr spdr f7 e8 ef e0 acc e7 d8 s1con s1sta s1dat s1adr df d0 psw d7 c8 xramp cf c0 c7 b8 ip bf b0 b7 a8 ie af a0 a7 98 scon sbuf 9f 90 97 88 tcon tmod tl0 tl1 th0 th1 8f 80 sp dpl dph pcon 87 sfrs in this column are bit addressable [figure 6] sfr memory map note that in the sfr-map not all of the addres ses are occupied. unoccupied addresses are not im- plemented on the chip. read accesses to these un implemented sfr locations will in general return random data, and write accesses will have no effect. user software should not write 1s to these unim- plemented locations, since they may be used in ot her 80c51 family derivative products to invoke new features. there are two types of special func tions registers: regist ers, which are part of the cpu and often di- rectly used by certain instructions, and sfrs, whic h are implemented in peripheral blocks. the sfrs of the cpu are available in all derivatives of this microcontroller and are described in the text below. peripheral blocks are optional and so are the sfrs, which are implemented inside these peripherals. therefore the peripheral sfrs are described with the peripheral blocks in chapter 5.
handshake solutions HT80C51 user manual memory organization ? special function registers page 14 of 132 ? philips electronics n.v. 2005 2.5.1. accumulator acc acc is the accumulator register. the mnemonics for a ccumulator-specific instructions, however, refer to the accumulator simply as a . acc (a) accumulator addr = e0h reset value = 00h bits 7 6 5 4 3 2 1 0 acc 2.5.2. register b the b-register is used during multiply and divide o perations. for other instructions it can be treated as another scratch pad register. b register b addr = f0h reset value = 00h bits 7 6 5 4 3 2 1 0 b 2.5.3. program status word psw the program status word ( psw ) register contains program status information as detailed below. psw program status word addr = d0h reset value = 00h bits 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov - p bit symbol function psw.7 cy carry flag. psw.6 ac auxiliary carry flag. psw.5 f0 flag 0 available to the user for general purpose. psw.4 psw.3 rs1 rs0 0 0 0 1 1 0 1 1 register bank selector bit 1. register bank selector bit 0. (rs1, rs0) select the register bank as follows: bank 0 ( 00h .. 07h ) bank 1 ( 08h .. 0fh ) bank 2 ( 10h .. 17h ) bank 3 ( 18h .. 1fh ) psw.3 rs0 register bank selector bit 0 (see note). psw.2 ov overflow flag. psw.1 - usable as a general-purpose flag. psw.0 p parity flag. set/cleared by hardwa re each instruction cycle to indicate an odd/even number of ?1? bits in the accumulator, that means even parity. 2.5.4. stack pointer sp the stack pointer ( sp ) register is 8 bits wide. it is incr emented before data is stored during push and call executions. while the stack may reside anywhere in on-chip ram, the stack pointer is initialized to 07h after a reset. this causes the stack to begin at locations 08h .
HT80C51 user manual memory organization ? special function registers handshake solutions ? philips electronics n.v. 2005 page 15 of 132 sp stack pointer addr = 81h reset value = 07h bits 7 6 5 4 3 2 1 0 sp 2.5.5. data pointer dptr dph dpl the data pointer ( dptr ) consists of a high byte ( dph ) and a low byte ( dpl ). its intended function is to hold a 16-bit address for movx and movc instructions . it may be manipulated as a 16-bit register or as two independent 8-bit registers. dph data pointer high byte addr = 83h reset value = 00h bits 7 6 5 4 3 2 1 0 dph dpl data pointer low byte addr = 82h reset value = 00h bits 7 6 5 4 3 2 1 0 dpl 2.5.5.1. dual data pointer (option HT80C51_cpu_dualdptr) optional two data pointer registers can be implemented, dptr0 and dptr1 . only one data pointer can be used at a time. this can be selected by bit dps in sfr pcon (see below). all instructions using the dptr , dpl or dph use either dptr0 or dptr1 as selected by sfr bit dps . the dps bit should be saved by software when switching between dptr0 and dptr1 within procedures or interrupt routines. 2.5.6. power saving modes pcon the HT80C51 has two power reducing modes, idle and power down. the input through which backup power is supplied during these operations is vdd . in the idle mode ( idl = 1 ), the oscillator continue s to run and the interrup t, serial port, and timer blocks continue to be clocked, but the clock signal is gated off to the cpu. in power down ( pd = 1 ), the oscillator is frozen. since switching on or off the oscillator is done outside the microcontroller, dedicated output pins indi- cate idle mode ( cpu_idle_o ) and power down ( cpu_powerdown_o ). external circuits needs to ob- serve these signals to switch off the clocks (i n power down) or to change the supply voltage. setting bits in special function register pcon activate the idle and power down modes.
handshake solutions HT80C51 user manual memory organization ? special function registers page 16 of 132 ? philips electronics n.v. 2005 pcon power control register addr = 87h reset value = 0xx00000 bits 7 6 5 4 3 2 1 0 smod - - (dps) gf1 gf0 pd idl bit symbol function pcon.7 smod 1: 0: double baud rate (see chapter 5.3 ?standard serial interface?) if timer 1 is used to generate the baudrate and the serial interface is used in modes 1, 2 or 3, then the baudrate is doubled. the baudrate is not influenced pcon.6 pcon.5 - reserved (write 0, reads 0) pcon.4 (dps) 1: 0: data pointer select; implemented with dual data pointer option, only, otherwise reserved bit (write 0, reads 0) select dptr1 for all dptr accesses (and for dpl and dph ) select dptr0 for all dptr accesses (and for dpl and dph ) pcon.3 gf1 general-purpose flag bit. pcon.2 gf0 general-purpose flag bit. pcon.1 pd power-down bit. setting this bit activates power-down operation, which is also indicated at output pin cpu_powerdown_o . pcon.0 idl idle mode bit. setting this bi t activates idle mode operation, which is also indicated at output pin cpu_idle_o . note: if 1s are written to pd and idl at the same time, pd takes precedence. user software should never write 1s to unimplement ed bits, since they may be used in other 80c51 family products. 2.5.6.1. idle mode an instruction that sets pcon.0 immediately switches into the idle mode, so no further instruction is executed. the clock signal is gated off from the cpu but not to the timer and serial port functions. the cpu status is preserved in its entirety; the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle. the port pins hold the logical states they had at the time idle was activated. there are two ways to terminate the idle. activation of any enabl ed interrupt will cause pcon.0 to be cleared by hardware, terminating the idle mode. the interrupt will be serviced, and following reti , the next instruction to be executed will be the one following the instruction that put the device into idle. the flag bits gf0 and gf1 can be used to give an indication if an interrupt occurred during normal op- eration or during an idle. for example, an instruction that activates idle can also set one or both flag bits. when idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. the other way of terminating the idle mode is with a hardware reset, which starts the processor in the same manner as a power-on reset. 2.5.6.2. power-down mode an instruction that sets pcon.1 immediately switches into the power down mode. in the power down mode, the cpu clock and all peripheral clocks ca n be stopped completely to lower the power con- sumption. this has to be done be external circuits, which observe the output pin cpu_powerdown_o , that indicates the power down mode. with the clocks frozen, all functions are stopped, the contents of the on-chip ram and special function registers are ma intained. the port pins output the values held by their respective sfrs. the only exit from power down is a hardware reset. reset redefines all the sfrs, but does not change the on-chip ram.
HT80C51 user manual memory organization ? movc protection (option HT80C51_cpu_movcp) handshake solutions ? philips electronics n.v. 2005 page 17 of 132 in the power down mode of operati on, vdd can be reduced to a level that is still sufficient for logic and ram to keep their contents. care must be take n, however, to ensure that vdd is not reduced before the power down mode is invoked, and that v dd is restored to its normal operating level, be- fore the power down mode is terminated. the reset that terminates power down also should switch on the core clock again. the reset should not be acti vated before vdd is restor ed to its normal operat- ing level, and must be held active long enough to allow an oscillator to restart and stabilize. 2.5.7. external ram page xramp (option HT80C51_cpu_xramp) the movx-instruction comes in two flavors: movx @dptr and movx @ri . for the second version ( movx @ri ) the contents of one index register ri specify the lower half of the 16bit address for the access to the external data memory. the upper half is not specified by the instruction, but the sfr xramp supplies it. in other words, the external data memory is divided into pages of 256bytes, with xramp selecting the page and @ri addressing within this page. xramp external ram page addr = c9h reset value = 00h bits 7 6 5 4 3 2 1 0 xramp 2.6. movc protection (option HT80C51_cpu_movcp) this optional feature protects a memory region in program memory from being read out by a program outside this region. thus any movc instruction, t hat is executed outside the protected region and tries to access the protected regi on, will return the value 00h instead of the real memory content. the pro- tection is only one-way, so a protected progra m can read the complete program memory area. the protected region is defined to start at address 0000h . the upper limit of the protected region is defined by static inputs HT80C51_movcp_uaddr_i , so the protected code memory region is from 0000h <= addr < HT80C51_movcp_uaddr_i . the value of this upper limit is under control of the customer, but must not change during execution. us ually it is hard wired to a constant value.
handshake solutions HT80C51 user manual reset page 18 of 132 ? philips electronics n.v. 2005 3. reset the reset input is the z_r pin. an asynchronous reset is accomplished by holding the z_r pin low. the minimum low time is not depending on the clock frequency but it depends on the standard cell library, placement and routing. however, usually a reset pulse of about 100ns is sufficient. a reset initializes most of the sf rs. the following table lists the sfr reset values. the internal ram is not affected by reset. on power up the ram content is not defined. register reset value pc acc b psw sp dptr pcon ien0 ien1 ip0 ip1 tmod tcon th0 tl0 th1 tl1 scon sbuf pout0 pout1 pout2 pout3 s1con s1sta s1dat s1adr spcr spsr spdr dcon dkey dtxt 0000h 00h 00h 00h 07h 0000h 0xx0 000 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h xx ffh ffh ffh ffh 00h f8h 00h 00h 0000 0100 00h 00h xx xx xx note: ?xx? means no initialization on reset. [table 1] 80c51 sfr reset values
HT80C51 user manual clocks ? cpu cock handshake solutions ? philips electronics n.v. 2005 page 19 of 132 4. clocks 4.1. cpu cock 4.1.1. clockless (aynchronous) cnfiguration a handshake circuit does not require a clock to wo rk, it simply adapts its speed to the environment (other blocks, supply voltage, temperature, etc.). this is a complete asynchronous mode of operation and our standard configuration of the core. 4.1.2. clock synchronization (option HT80C51_cpu_sync) some applications or programs require a precisel y defined timing behavior of the instruction execu- tion, for instance, when timing or waiting loops are used. for this case an optional synchronization feature is offered. with this feature come two additional input pins: cpu_clk_i and cpu_sync_i . cpu_clk_i delivers the machine clock and thus the speed of the cpu, input cpu_sync_i decides, whether the cpu should be synchronized to cpu_clk_i or not: ? in synchronous mode ( cpu_sync_i = 1 ), the cpu synchronizes with cpu_clk_i on a machine cycle basis after each instruction in such a way t hat the number of clock cycles for that instruc- tion is the same as the number of machine cy cles for a synchronous implementation. since there are no clock dividers attached, one cpu_clk_i cycle equals to one machine cycle. ? in asynchronous mode of operation ( cpu_sync_i = 0 ), the cpu runs at it s natural speed, and a slow cpu_clk_i does not slow it down. 4.2. peripheral clocks in a traditional (synchronous) 80c51 system, all cloc ks for peripherals are derived from the clock for the cpu or from the cpu?s machine cycle, which is usually 1/12 or 1/6 of the cpu clock frequency, depending on the implementation of the cpu. hence a ll timing specifications like timer overflow times or baud rates were specified in relation to the cpu clock. in a handshake design no single, global clock sour ce is needed, the clock for the cpu can even be omitted (which is the standard configuration for t he HT80C51). thus for each peripheral that needs a clock, e.g. timers, serial interf aces or the synchronous sfr bus, a dedicated clock input is provided. so the optimum clock frequency can be supplied to each peripheral, completely independent from all other clock frequencies. also note, that there is no internal clock di vider implemented (divide by 12 or 6). thus, compared to a synchronous design, the same timings (e.g. baud rates) can be achieved with a lower input clock frequency resulting in lower power consumption. the timing specifications of the peripherals are re lated to their specific input clock frequencies.
handshake solutions HT80C51 user manual peripheral modules ? interrupt controller page 20 of 132 ? philips electronics n.v. 2005 5. peripheral modules for the HT80C51 a number of standard peripherals lik e timers and serial interfaces exist. they are compatible to the standard peripherals in synchr onous implementations. the peripherals can be or- dered along with the cpu and are then part of a co mbined delivery. the following chapters describe these peripherals in detail with further options (if available) and their sfrs. 5.1. interrupt controller this module handles the enabling and priority decoding of interrupt requests as well as entering and leaving the interrupt routines. the number of inte rrupt inputs can be configured from 0 up to 15. 5.1.1. options the interrupt controller can be ordered by option HT80C51_int . the number of interrupt inputs int_req_i can be selected (ordered) by using option HT80C51_int_count . 5.1.2. special function registers (ien0 ien1 ip0 ip1) the number of implemented sfrs for the interrupt c ontroller and even the number of bits within these sfrs depends on the selected number of in terrupt inputs. for each interrupt input int_req_i[x] one interrupt enable bit and one interrupt priority bit ex ists. all interrupt enable bits are collected in two sfrs: ien0 and ien1 . all interrupt priority bits ar e collected in further two sfrs: ip0 and ip1 . if the number of interrupt inputs is greater than 0, sfrs ien0 and ip0 exist. if the number of interrupt inputs is greater than 7, sfrs ien1 and ip1 exist, too. ien0 (ie) interrupt enable register 0 addr = a8h reset value = 00h bits 7 6 5 4 3 2 1 0 ea ien0.6 es1 es0 et1 ex1 et0 ex0 bit symbol function ien0.7 ea 1: 0: general enable/disable control. if ea = 0 , any individually enabled interrupt will be accepted. no interrupt is enabled. ien0.6 enable interrupt input int_req_i[6] . ien0.5 es1 enable i2c interrupt (if available) or interrupt input int_req_i[5] . ien0.4 es0 enable uart interrupt (if available) or interrupt input int_req_i[4] . ien0.3 et1 enable timer 1 overflow inte rrupt (if available) or interrupt input int_req_i[3] . ien0.2 ex1 enable external interrupt from timer 1 ( ie1 ) (if available) or interrupt input int_req_i[2] . ien0.1 et0 enable timer 0 overflow inte rrupt (if available) or interrupt input int_req_i[1] . ien0.0 ex0 enable external interrupt from timer 0 ( ie0 ) (if available) or interrupt input int_req_i[0] . bit values: 0 = interrupt disabled; 1 = interrupt enabled.
HT80C51 user manual peripheral modules ? interrupt controller handshake solutions ? philips electronics n.v. 2005 page 21 of 132 ien1 interrupt enable register 1 addr = e8h reset value = 00h bits 7 6 5 4 3 2 1 0 ien1.7 ien1.6 ien1.5 ien1.4 ien1.3 ien1.2 ien1.1 ien1.0 bit symbol function ien1.7 enable interrupt input ?int_req_i[14]?. ien1.6 enable interrupt input ?int_req_i[13]?. ien1.5 enable interrupt input ?int_req_i[12]?. ien1.4 enable interrupt input ?int_req_i[11]?. ien1.3 enable interrupt input ?int_req_i[10]?. ien1.2 enable interrupt input ?int_req_i[9]?. ien1.1 enable interrupt input ?int_req_i[8]?. ien1.0 enable interrupt input ?int_req_i[7]?. bit values: 0 = interrupt disabled; 1 = interrupt enabled. ip0 (ip) interrupt priority register 0 addr = b8h reset value = 00h bits 7 6 5 4 3 2 1 0 - ip0.6 ps1 ps0 pt1 px1 pt0 px0 bit symbol function ip0.7 - reserved. ip0.6 priority level for interrupt input int_req_i[6] . ip0.5 es1 priority level for i2c interrupt (if available) or interrupt input int_req_i[5] . ip0.4 es0 priority level for uart inte rrupt (if available) or interrupt input int_req_i[4] . ip0.3 et1 priority level for timer 1 overflow interrupt (if available) or interrupt input int_req_i[3] . ip0.2 ex1 priority level for external interrupt from timer 1 ( ie1 ) (if available) or interrupt input int_req_i[2] . ip0.1 et0 priority level for timer 0 overflow interrupt (if available) or interrupt input int_req_i[1] . ip0.0 ex0 priority level for external interrupt from timer 0 ( ie0 ) (if available) or interrupt input int_req_i[0] . bit values: 0 = low priority; 1 = high priority.
handshake solutions HT80C51 user manual peripheral modules ? interrupt controller page 22 of 132 ? philips electronics n.v. 2005 ip1 interrupt priority register 1 addr = f8h reset value = 00h bits 7 6 5 4 3 2 1 0 ip1.7 ip1.6 ip1.5 ip1.4 ip1.3 ip1.2 ip1.1 ip1.0 bit symbol function ip1.7 priority level for interrupt input int_req_i[14] . ip1.6 priority level for interrupt input int_req_i[13] . ip1.5 priority level for interrupt input int_req_i[12] . ip1.4 priority level for interrupt input int_req_i[11] . ip1.3 priority level for interrupt input int_req_i[10] . ip1.2 priority level for interrupt input int_req_i[9] . ip1.1 priority level for interrupt input int_req_i[8] . ip1.0 priority level for interrupt input int_req_i[7] . bit values: 0 = low priority; 1 = high priority. 5.1.3. operation the HT80C51 provides up to 15 interrupt inputs. depending on the configuration of standard periph- erals, some of these inputs are already internally connected to interrupt sources in these peripherals. for a description of these interr upt sources, please, see the description of the peripheral blocks. [table 2] shows these default connections. all of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. that is, interrupts can be generated or pending inter- rupts can be canceled in software. each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in special function registers ien0 and ien1 . ien0 also contains a global disable bit, ea , which disables all interrupts at once. 5.1.3.1. interrupt priority level structure each interrupt source can also be individually programmed to one of two priority levels by setting or clearing a bit in special function registers ip0 and ip1 . a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-pr iority interrupt. a high-priority interrupt can?t be interrupted by any other interrupt source. if two requests of different priority levels are receiv ed simultaneously, the request of higher priority level is serviced. if requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second prior- ity structure determined by the polling sequence, as summarized in [table 2].
HT80C51 user manual peripheral modules ? interrupt controller handshake solutions ? philips electronics n.v. 2005 page 23 of 132 [table 2] interrupt signals, vectors and priorities. 5.1.3.2. how interrupts are handled the interrupt flags are sampled at every start of an instruction. the samples are polled at the start of the following instruction. if one of the flags was in a set conditi on at the preceding cycle, the polling cycle will find it and the inte rrupt system will generate an lcall to the appropriate service routine, provided this hardware-generated lcall is not blocked by any of the following conditions: 1. an interrupt of equal or higher pr iority level is already in progress. 2. the instruction in progress is reti or any write to the ienx or ipx registers. any of these two conditions will block the generation of the lcall to the in terrupt service routine. condition 2 ensures that if the instruction in progress is reti or any access to ienx or ipx , then at least one more instruction will be executed before any interrupt is vectored to. the polling cycle is repeated with each new instructio n, and the values polled are the values that were present at the start of the previous instruction. note that if an interrupt flag is active but not being re- sponded to for one of the above conditions, if the fl ag is not still active when the blocking condition is removed, the denied interrupt will not be serviced. in other words, the fact t hat the interrupt flag was once active but not serviced is not re membered. every polling cycle is new. interrupt interrupt input standard internal connection (if peripheral is selected) vector address enable priority select priority within level int 0 int_req_i[0] ie0 timer 0 0003h ien0.0 ip0.0 highest int 1 int_req_i[1] tf0 timer 0 000bh ien0.1 ip0.1 int 2 int_req_i[2] ie1 timer 1 0013h ien0.2 ip0.2 int 3 int_req_i[3] tf1 timer 1 001bh ien0.3 ip0.3 int 4 int_req_i[4] ri or ti si0(uart) 0023h ien0.4 ip0.4 int 5 int_req_i[5] si i2c 002bh ien0.5 ip0.5 int 6 int_req_i[6] spif spi 0033h ien0.6 ip0.6 int 7 int_req_i[7] 003bh ien1.0 ip1.0 int 8 int_req_i[8] 0043h ien1.1 ip1.1 int 9 int_req_i[9] 004bh ien1.2 ip1.2 int 10 int_req_i[10] 0053h ien1.3 ip1.3 int 11 int_req_i[11] 005bh ien1.4 ip1.4 int 12 int_req_i[12] 0063h ien1.5 ip1.5 int 13 int_req_i[13] 006bh ien1.6 ip1.6 int 14 int_req_i[14] 0073h ien1.7 ip1.7 lowest note: the ?priority within level? structure is only used to resolve simultaneous requests of the same priority level.
handshake solutions HT80C51 user manual peripheral modules ? interrupt controller page 24 of 132 ? philips electronics n.v. 2005 c1 c2 c3 c4 c5 machine cycle e interrupt goes active interrupt latched interrupts are poled long call to interrupt vector address interrupt routine this is the fastest possible response when c 2 is the final cycle of an instruction other t han reti or an access to ie or ip . [figure 7] interrupt response timing diagram the polling cycle/lcall sequence is illustrated in [figur e 7]. note that if an interrupt of higher priority level goes active prior to the instruction labeled c3 in [figure 7], then in accordance with the above rules it will be vectored to during c5 and c6, without any instruction of the lower priority routine having been executed. thus the processor acknowledges an interrupt requ est by executing a hardware-generated lcall to the appropriate servicing routine. in some cases it also clears the flag that generated the interrupt, and in other cases it doesn?t. it never clears the serial po rt flag. this has to be done in the user?s software. it clears an external interrupt flag ( ie0 or ie1 ) only if it was transition-activated. the hardware- generated lcall pushes the contents of the program counter on to the stack (but it does not save the psw ) and reloads the pc with an address that depen ds on the source of the interrupt being vec- tored to, as shown in column ?v ector address? in [table 2]. execution proceeds from that location until the reti instruction is encountered. the reti instruction informs the processor that this interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the program counter. ex ecution of the interrupted program continues from where it left off. note that a simple ret instructi on would also have return ed execution to the inter- rupted program, but it w ould have left the interrupt control system thinking an interrupt was still in pro- gress, making future interrupts impossible. 5.1.3.3. external interrupts the external sources can be programmed to be leve l-activated or transition-activated by setting or clearing bit it1 or it0 in register tcon . if itx = 0 , external interrupt x is triggered by a detected low at the t01_intx_n_i pin. if itx = 1 , external interrupt x is edge triggered. in this mode if the interrupt input ( t01_int0_n_i for it0 , t01_int1_n_i for it1 ) shows a high to low transition, interrupt request flag iex in tcon is set. flag bit iex then requests the interrupt. since t he external interrupt pins are not sampled, there is no minimum low duration specified. iex will be automatically cleared by the cpu when the service routine is called. if the external interrupt is level-activated, the exte rnal source has to hold the request active until the requested interrupt is actually generated. then it has to deactivate the request before the interrupt service routine is comple ted, or else another in terrupt will be generated. 5.1.3.4. response time the t01_int0_n_i and t01_int1_n_i levels are inverted and latched into ie0 and ie1 . the values are not actually polled by the circuitry until the next start of an instruction. if a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. t he call itself takes two cycles. thus, a minimum of three complete machine cycles elapse between acti vation of an external interrupt request and the beginning of execution of the first in struction of the service routine.
HT80C51 user manual peripheral modules ? interrupt controller handshake solutions ? philips electronics n.v. 2005 page 25 of 132 a longer response time would result if the request were blocked by one of the 2 previously listed con- ditions. if an interrupt of equal or higher priority leve l is already in progress, the additional wait time obviously depends on the nature of the other interrupt?s service routine. if the in struction in progress is not in its final cycle, the additional wait time cannot be more the 3 cycles, since the longest instructions (mul and div) are only 4 cycles long, and if the instruction in progress is reti or an access to ie or ip , the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete the instruction in progress, plus 4 cycles to comple te the next instruction if the instruction is mul or div). thus, in a single-interrupt system, the response ti me is always more than 3 cycles and less than 9 cycles. 5.1.4. setting up the interrupt controller to use any of the interrupts in the 80c51 fam ily, the following three steps must be taken. 1. set the ea (enable all) bit in the ie register to 1 . 2. set the corresponding individual interrupt enable bit in the ie register to 1 . 3. begin the interrupt service rout ine at the corresponding vector address of that interrupt (see [table 2]). in addition, for external interrupts (input pins t01_int0_n_i and t01_int1_n_i ) depending on whether the interrupt is to be level or transition activated, bits it0 or it1 in the tcon register may need to be set to 1 . itx = 0 level activated itx = 1 transition activated 5.1.4.1. assigning a higher priority to one or more interrupts in order to assign higher priority to an interrupt, the corresponding bit in the ipx register must be set to 1 . remember that while an interrupt service is in prog ress, it cannot be interrupted by a lower or same level interrupt.
handshake solutions HT80C51 user manual peripheral modules ? timers 0 and 1 page 26 of 132 ? philips electronics n.v. 2005 5.2. timers 0 and 1 this module comprises two 16bit timers/counters: timer0 and timer1. both can be configured to oper- ate either as timers or event counters. in the ?timer? function, the register is incr emented every timer clock cycle (clock input t01_clk_i ). thus, if the operation of the cpu is synchronized to the same clock, one can think of it as counting machine cycles of the cpu. in the ?counter? function, the register is incremented in response to a 1-to-0 transition at its corre- sponding external input pin, t0_count_i or t1_count_i . by design there are no restrictions on the duty cycle or the frequency of the external input signals. however, depending on the standard cell library, that is used, and the actual layout some maximum limits will apply. 5.2.1. options this module can be enabled (ordered) by using option HT80C51_t01 . 5.2.2. special function registers (tmod tcon tl0 tl1 th0 th1) tmod timer/counter mode control addr = 89h reset value = 00h bits 7 6 5 4 3 2 1 0 gate1 c/t1 t1m1 t1m0 gate0 c/t0 t0m1 t0m0 bit symbol function tmod.7 gate1 1: 0: timer 1 gating control timer/counter 1 is enabled only while input pin t01_int1_n_i is high and tr1 ( tcon ) is 1 . timer/counter 1 is enabled if tr1 is set. tmod.6 c/t1 1: 0: timer 1 operation selection counter operation (clock source is input pin t1_count_i ) timer operation (clock source is the clock input t01_clk_i ) tmod.5 tmod.4 t1m1 t1m0 00: 01: 10: 11: timer 1 mode selection 8048 timer mode, tl1 serves as a 5bit prescaler 16bit timer/counter: th1 and tl1 are cascaded; no prescaler 8bit auto-reload timer/counter: th1 holds the value which is loaded into tl1 each time it overflows stopped tmod.3 gate0 1: 0: timer 0 gating control timer/counter 0 is enabled only while input pin t01_int0_n_i is high and tr0 ( tcon ) is 1. timer/counter 1 is enabled if tr0 is set. tmod.2 c/t0 1: 0: timer 0 operation selection counter operation (clock source is input pin t0_count_i ) timer operation (clock source is the clock input t01_clk_i ) tmod.1 tmod.0 t0m1 t0m0 00: 01: 10: 11: timer 0 mode selection 8048 timer mode, tl0 serves as a 5bit prescaler 16bit timer/counter: th0 and tl0 are cascaded; no prescaler 8bit auto-reload timer/counter: th0 holds the value which is loaded into tl0 each time it overflows tl0 is an 8bit timer/counter controlled by standard timer 0 control bits. th0 is a further 8bit timer cont rolled by timer 1 control bits.
HT80C51 user manual peripheral modules ? timers 0 and 1 handshake solutions ? philips electronics n.v. 2005 page 27 of 132 tcon timer/counter control addr = 88h reset value = 00h bits 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit symbol function tcon.7 tf1 timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. tcon.6 tr1 1: 0: timer 1 run control bit. set/cleared by software to turn timer 1 on/off. timer 1 on. timer 1 off. tcon.5 tf0 timer 0 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. tcon.4 tr0 1: 0: timer 0 run control bit. set/cleared by software to turn timer 1 on/off. timer 0 on. timer 0 off. tcon.3 ie1 interrupt 1 edge flag. set by hardware when external interrupt is de- tected. cleared when interrupt is processed. tcon.2 it1 1: 0: interrupt 1 type control bit. external interrupt t01_int1_n_i is edge sensitive (falling edge). external interrupt t01_int1_n_i is level sensitive (low level). tcon.1 ie0 interrupt 0 edge flag. set by hardware when external interrupt is de- tected. cleared when interrupt is processed. tcon.0 it0 1: 0: interrupt 0 type control bit. external interrupt t01_int0_n_i is edge sensitive (falling edge). external interrupt t01_int0_n_i is level sensitive (low level). tl0 timer 0 counter register, low byte addr = 82h reset value = 00h bits 7 6 5 4 3 2 1 0 tl0 th0 timer 0 counter register, high byte addr = 84h reset value = 00h bits 7 6 5 4 3 2 1 0 th0 tl1 timer 1 counter register, low byte addr = 83h reset value = 00h bits 7 6 5 4 3 2 1 0 tl1 th1 timer 1 counter register, high byte addr = 85h reset value = 00h bits 7 6 5 4 3 2 1 0 th1
handshake solutions HT80C51 user manual peripheral modules ? timers 0 and 1 page 28 of 132 ? philips electronics n.v. 2005 5.2.3. interrupts each of the timers can generate two separate interr upt signals, which are directly connected to inter- rupt request lines of the interrupt controller. the fo llowing table and [figure 8] describe these sources and connections. for interrupt priorities and interrupt vectors see the description of the interrupt con- troller. interrupt source description interrupt signal timer 0: ie0 set by hardware when external interrupt t01_int0_n_i is detected. if sfr bit it0 is set, the flag is set on a falling edge of the external interrupt, if it0 is cleared, a low level on the external interrupt line cause an interrupt. cleared when interrupt is processed. int0 tf0 timer 0 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. int1 timer 1: ie1 set by hardware when external interrupt t01_int1_n_i is detected. if sfr bit it1 is set, the flag is set on a falling edge of the external interrupt, if it1 is cleared, a low level on the external interrupt line cause an interrupt. cleared when interrupt is processed. int2 tf1 timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. int3 ie1 t01_int1_n_i it1 0 1 ie0 t01_int0_n_i it0 0 1 tf0 tf1 int0 int1 int2 int3 [figure 8] interrupt sources from the timers 0 and 1
HT80C51 user manual peripheral modules ? timers 0 and 1 handshake solutions ? philips electronics n.v. 2005 page 29 of 132 5.2.4. operation the timer- or counter-function is selected by control bits c/tx in the special function register tmod . these two timer/counters have four operating modes, which are selected by bit-pairs ( m1 , m0 ) in tmod . modes 0, 1, and 2 are the same for both timers/counters. mode 3 is different. the four operating modes are described in the following text. 5.2.4.1. mode 0 putting either timer into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a di- vide-by-32 prescaler.[figure 9] shows the m ode 0 operation as it applies to timer 1. in this mode, the timer register is configured as a 13 -bit register. as the count rolls over from all 1s to all 0s, it sets the timer interrupt flag tf1 . the counted input is enabled to the timer when tr1 = 1 and either gate1 = 0 or pin t01_int1_n_i = 1 . setting gate1 = 1 allows the timer to be controlled by external input t01_int1_n_i , to facilitate pulse width measurements). tr1 is a control bit in the spe- cial function register tcon . gate1 is in tmod . the 13-bit register consists of all 8 bits of th1 and the lower 5 bits of tl1 . the upper 3 bits of tl1 are indeterminate and should be ignored. setting the run flag ( tr1 ) does not clear the registers. mode 0 operation is the same for the timer 0 as for timer 1. substitute tr0 , tf0 , gate0 , c/t0 , t0_count_i and t01_int0_n_i for the corresponding timer 1 signals in [figure 9]. t 0 1_clk_i t1_count_i t01_int1_n_i gate 1 tr1 th1 (5 bits) th1 (8 bits) tf1 interrupt control c/t1=1 c/t1=0 [figure 9] timer/counter mode 0: 13bit counter 5.2.4.2. mode 1 mode 1 is the same as mode 0, except that the timer register is being run with all 16 bits. 5.2.4.3. mode 2 mode 2 configures the timer register as an 8bit counter ( tl1 ) with automatic reload, as shown in [figure 10]. overflow from tl1 not only sets tf1 , but also reloads tl1 with the contents of th1 , which is preset by software. the reload leaves th1 unchanged. mode 2 operation is the same for timer/counter 0.
handshake solutions HT80C51 user manual peripheral modules ? timers 0 and 1 page 30 of 132 ? philips electronics n.v. 2005 t 0 1_clk_i t1_count_i t01_int1_n_i gate 1 tr1 tl1 (8 bits) tf1 interrupt control c/t1=1 c/t1=0 th1 (8 bits) reload [figure 10] timer/counter mode 2: 8bit auto-reload . 5.2.4.4. mode 3 timer 1 in mode 3 simply holds its count. the effect is the same as setting tr1 = 0 . timer 0 in mode 3 establishes tl0 and th0 as two separate counters. the logic for mode 3 on timer 0 is shown in [figure 11]. tl0 uses the timer 0 control bits: c/t0 , gate0 , tr0 , t01_int0_n_i and tf0 . th0 is locked into a timer function (counting timer clocks t01_clk_i ) and takes over the use of tr1 and tf1 from timer 1. thus, th0 now controls the ?timer 1? interrupt. mode 3 is provided for applications requiring an extra 8-bit timer on the counter. with timer 0 in mode 3, an 80c51 can look like it has three timer/counter s. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mo de 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt. t 0 1_clk_i t0_count_i t01_int0_n_i gate 0 tr0 tl0 (8 bits) tf0 int 1 control c/t0=1 c/t0=0 t01_clk_i tr1 th0 (8 bits) tf1 int 3 [figure 11] timer/counter 0 mode 3: two 8bit counters .
HT80C51 user manual peripheral modules ? timers 0 and 1 handshake solutions ? philips electronics n.v. 2005 page 31 of 132 5.2.5. setting up the timers [table 3] and [table 4] give some values for tmod , which can be used to set up timer 0 in different modes. for these tables it is assumed that only one timer is being used at a time. if it is desired to run timers 0 and 1 simultaneously, in any mode, the value in tmod for timer 0 must be ored with the value shown for timer 1 ([table 5] and [table 6]). for example, if it is desired to run timer 0 in mode 1 gate (external control), and timer 1 in mode 2 counter , then the value that must be loaded into tmod is 69h ( 09h from [table 3] ored with 60h from [table 6]). moreover, it is assumed that the user , at this point, is not ready to turn the timers on and will do that at a different point in the program by setting bit trx (in tcon ) to 1 . 5.2.5.1. timer/counter 0 tmod mode timer 0 function internal control (note 1) external control (note 2) 0 1 2 3 13bit timer 16bit timer 8bit auto-reload two 8bit timers 00h 01h 02h 03h 08h 09h 0ah 0bh [table 3] timer 0 as a timer tmod mode timer 0 function internal control (note 1) external control (note 2) 0 1 2 3 13bit timer 16bit timer 8bit auto-reload two 8bit timers 04h 05h 06h 07h 0ch 0dh 0eh 0fh [table 4] timer 0 as a counter notes: 1. the timer is turned on/off by setting/clearing bit tr0 in the software. 2. the timer is turned on, if both t01_int0_n_i = 1 and tr0 = 1 (hardware control).
handshake solutions HT80C51 user manual peripheral modules ? timers 0 and 1 page 32 of 132 ? philips electronics n.v. 2005 5.2.5.2. timer/counter 1 tmod mode timer 1 function internal control (note 1) external control (note 2) 0 1 2 3 13bit timer 16bit timer 8bit auto-reload two 8bit timers 00h 10h 20h 30h 80h 90h a0h b0h [table 5] timer 1 as a timer tmod mode timer 1 function internal control (note 1) external control (note 2) 0 1 2 3 13bit timer 16bit timer 8bit auto-reload two 8bit timers 40h 50h 60h 70h c0h d0h e0h f0h [table 6] timer 1 as a counter notes: 1. the timer is turned on/off by setting/clearing bit tr1 in the software. 2. the timer is turned on, if both t01_int0_n_i = 1 and tr0 = 1 (hardware control).
HT80C51 user manual peripheral modules ? standard serial interface (sio0) handshake solutions ? philips electronics n.v. 2005 page 33 of 132 5.3. standard serial interface (sio0) this module implements a buffered, full duplex asyn chronous serial interface with multimaster sup- port. 5.3.1. options this module can be enabled (ordered) by using option HT80C51_sio . 5.3.2. special function registers (scon sbuf smod) scon serial port control register addr = 98h reset value = 00h bits 7 6 5 4 3 2 1 0 sm0 sm1 sm2 ren tb8 rb8 ti ri bit symbol function scon.7 scon.6 sm0 sm1 00: 01: 10: 11: serial mode selection: ( sm0 , sm1 ): mode 0: shift register f sio_clk_i mode 1: 8bit uart depending on f t01_overflow mode 2: 9bit uart f sio_clk_i /64 or f sio_clk_i /32 mode 3: 9bit uart depending on f t01_overflow scon.5 sm2 multiprocessor communication in modes 2 and 3. if sm2 = 1 in modes 2 and 3, then ri will not be activated if the received 9 th data bit ( rb8 ) is 0 . if sm2 = 1 in mode 1, then ri will not be activated if a valid stop bit was not received. in mode 0 sm2 should be 0 . scon.4 ren enables serial reception. set by software to enable reception. clear by software to disable reception. scon.3 tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. scon.2 rb8 in modes 2 and 3, is the 9th data bit that was received. in mode 1, it sm2 = 0 , rb8 is the stop bit that was received. in mode 0, rb8 is not used. scon.1 ti transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software. scon.0 ri receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2 ). must be cleared by software. the serial port control and status regi ster is the special function register scon . this register contains not only the mode selection bits, but also the 9th data bit for transmit and receive ( tb8 and rb8 ), and the serial port interrupt bits ( ti and ri ). sbuf serial port buffer addr = 99h reset value = xx bits 7 6 5 4 3 2 1 0 sbuf the serial port receive and tran smit registers are both accessed thru special function register sbuf . writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register.
handshake solutions HT80C51 user manual peripheral modules ? standard serial interface (sio0) page 34 of 132 ? philips electronics n.v. 2005 pcon power control register addr = 87h reset value = 0xxx0000 bits 7 6 5 4 3 2 1 0 smod gf1 gf0 pd idl bit symbol function pcon.7 smod 1: 0: double baud rate if timer 1 is used to generate the baudrate and the serial interface is used in modes 1, 2 or 3, then the baudrate is doubled. the baudrate is not influenced pcon.6..0 see description of pcon register in cpu section. 5.3.3. interrupts the serial interface has two flags to indicate interrupt conditions: ti for transmit interrupts and ri for receive interrupts. however, there is only one interrupt output, that has to be shared by these interrupt sources. so, if any of the flags ti and ri is set, an interrupt request will be generated. the software has to check, then, which source was the cause. interrupt source description interrupt signal uart: ti ri transmit interrupt flag. receive interrupt flag. the logical or of ti and ri generates the interrupt request signal. int4 note: to comply with the standard specification, the serial interface does not support transmit- buffering. so the transmit interrupt is issued when the transmission has been completed (instead of as soon as the contents of sbuf are copied to the transmit shift register). interrupt flags are set by hardware and have to be reset by software. 5.3.4. operation the uart function is full duplex, meaning it can tr ansmit and receive simultaneously. it is also re- ceive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (however, if t he first byte still hasn?t been read by the time re- ception of the second byte is complete, one of t he bytes will be lost.) the serial port receive and transmit registers are both accessed thru special function register sbuf . writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register. 5.3.4.1. overview operating modes the serial port can operate in 4 modes: mode 0: serial data enters at input pin sio_rxd_i and exits through output pin sio_txd_o . pin sio_clk_o outputs the shift clock during transmission. 8 bits are transmitted/received (lsb first). the baud rate is fixed at the clock input sio_clk_i . this mode is restricted to half duplex operation only.
HT80C51 user manual peripheral modules ? standard serial interface (sio0) handshake solutions ? philips electronics n.v. 2005 page 35 of 132 mode 1: 10 bits are transmitted (through sio_txd_o ) or received (through sio_rxd_i ): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in spe- cial function register scon . the baud rate is derived from t he overflow rate of timer 1. mode 2: 11 bits are transmitted (through sio_txd_o ) or received (through sio_rxd_i ): start bit (0), 8 data bits (lsb first), a programmable 9t h data bit, and a stop bit (1). on transmit, the 9th data bit ( tb8 in scon ) can be assigned the value of 0 or 1 . or, for example, the parity bit ( p , in the psw ) could be moved into tb8 . on receive, the 9th data bit goes into rb8 in special function register scon , while the stop bit is ignored. the baud rate is pro- grammable to either 1/32 or 1/64 of the clock input sio_clk_i . mode 3: 11 bits are transmitted (through sio_txd_o ) or received (through sio_rxd_i ): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is de- rived from the overflow rate of timer 1. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1 . reception is initiated in the other modes by the incoming start bit if ren = 1 . 5.3.4.2. baud rates the baud rate in mode 0 has a fixed relation to the clock input sio_clk_i : mode 0 baud rate = sio_clk_i f the baud rate in mode 2 depends on the value of bit smod in special function register pcon . if smod = 0 (which is the value on reset), the baud rate is 1/64 of the frequency on clock input sio_clk_i . if smod = 1 , the baud rate is 1/32 of the frequency at sio_clk_i . mode 2 baud rate = sio_clk_i 64 2 f smod the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate. 5.3.4.3. using timer 1 to generate baud rates when timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod as follows: mode 1, 3 baud rate = ) 1 ( 32 2 rate overflow timer smod the timer 1 interrupt should be disabled in this app lication. the timer itself can be configured for either ?timer? or ?counter? operation, and in any of its 3 running modes. in the most typical applications, it is configured for ?timer? operation, in the auto-reload mode (high nibble of tmod = 0010b ). in that case the baud rate is given by the formula: mode 1, 3 baud rate = () 1 256 32 2 _ _ 01 th f i clk t smod ? one can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, and con- figuring the timer to run as a 16-bit timer (high nibble of tmod = 0001b ), and using the timer 1 inter- rupt to do a 16-bit software reload. [table 7] lists various commonly used baud rates and how they can be obtained from timer 1.
handshake solutions HT80C51 user manual peripheral modules ? standard serial interface (sio0) page 36 of 132 ? philips electronics n.v. 2005 timer 1 sio mode baud rate clock input clock frequency smod c/t1 mode reload value 0 2m sio_clk_i 2 mhz x x x x 2 625k t01_clk_i 20 mhz 1 x x x 1, 3 691.2k t01_clk_i 11.059 mhz 1 0 2 ffh 1, 3 345.6k t01_clk_i 11.059 mhz 1 0 2 feh 1, 3 230.4k t01_clk_i 11.059 mhz 1 0 2 fdh 1, 3 115.2k t01_clk_i 11.059 mhz 1 0 2 fah 1, 3 115.2k t01_clk_i 1.8432 mhz 1 0 2 ffh 1, 3 19.2k t01_clk_i 0.9216 mhz 1 0 2 fdh 1, 3 19.2k t01_clk_i 1.8432 mhz 1 0 2 fah 1, 3 9.6k t01_clk_i 1.8432 mhz 0 0 2 fah 1, 3 4.8k t01_clk_i 1.8432 mhz 0 0 2 f4h 1, 3 2.4k t01_clk_i 1.8432 mhz 0 0 2 e8h 1, 3 1.2k t01_clk_i 1.8432 mhz 0 0 2 d0h 1, 3 137.5 t01_clk_i 1 mhz 0 0 2 1dh 1, 3 110 t01_clk_i 0.5 mhz 0 0 2 72h 1, 3 110 t01_clk_i 1.8432 mhz 0 0 1 fdf4h [table 7] timer 1 generated commonly used baud rates 5.3.4.4. more about mode 0 serial data enters at input pin sio_rxd_i and exits through output pin sio_txd_o . pin sio_clk_o outputs the shift clock during transmission. 8 bits are transmitted/received (lsb first). the baud rate is fixed at the clock input sio_clk_i .[figure 12] shows a simplified functional diagram of the serial port in mode 0. this mode should be used in half duplex operation only. transmission is initiated by any instruction that uses sbuf as a destination register. send enables the output of the shift register to be routed to output pin sio_txd_o and also enables shift clock to the output pin sio_clk_o . the output data is always stable on the rising edge of the shift clock. every clock cycle in which send is active, the contents of the transmit shift are shifted to the right one posi- tion. reception is initiated by the condition ren = 1 and ri = 0 . receive enables the shift clock to the out- put pin sio_clk_o . the input data on pin sio_rxd_i is sampled on the falling edge of the shift clock. every clock cycle in which receive is active, the contents of the receive shift register are shifted to the left one position. at the 8th shift clock cycle ri is set (and receive is cleared) clearing bit ren during reception immediately stops the receiver.
HT80C51 user manual peripheral modules ? standard serial interface (sio0) handshake solutions ? philips electronics n.v. 2005 page 37 of 132 sbuf read only sbuf write only ht-sfr bus sio_rxd_i sio_txd_o ti >=1 & ri >=1 & sio _clk_o int[4] sio_clk_i sio_active_o sio_mode0_o 1 send receive notri ren receive [figure 12] block diagram of serial interface in mode 0 5.3.4.5. more about mode 1 10 bits are transmitted (through sio_txd_o ) or received (through sio_rxd_i ): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in special function register scon . the baud rate is derived from the overflow rate of timer 1. [figure 13]shows a simplified func- tional diagram of the serial port in mode 1. transmission is initiated by any instruction that uses sbuf as a destination register. transmission actually commences immediately after the next roll over in the divide-by-16 counter. (thus, the bit times are synchronized to the divide-by -16 counter, not to the ?write to sbuf ? signal.) after sending the start-bit and 8 data bits, the ti bit is set and the stop-bit is sent. reception is initiated by the detec tion of a 1-to-0 transition at sio_rxd_i . for this purpose sio_rxd_i is sampled at a rate of 16 times whatever baud rate has been established. when a transi- tion is detected, the divide-by-16 c ounter is immediately reset, thus it aligns its rollovers with the boundaries of the incoming bit times. at the 7th, 8t h, and 9th counter states of each bit time, the bit detector samples the value of sio_rxd_i . the value accepted is the value that was seen in at least 2 of the 3 samples. this is done for noise rejection. if the value accepted during the first bit time is not 0 ,
handshake solutions HT80C51 user manual peripheral modules ? standard serial interface (sio0) page 38 of 132 ? philips electronics n.v. 2005 the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. this is to provide rejection of false start bits. after the 8 data bits and the stop-bit have been received, the result is loaded into sbuf and rb8 , and ri is set to 1 , but that is only done, if the following conditions are met: 1. ri = 0 , and 2. either sm2 = 0 , or the received stop bit = 1 . if either of these two conditions is not met, the received frame is irretrievably lost. if both conditions are met, the stop bit goes into rb8 , the 8 data bits go into sbuf , and ri is activated. then the unit goes back to looking for a 1-to-0 transition in sio_rxd_i . 5.3.4.6. more about modes 2 and 3 these modes are very similar to mode 1, with the ma in difference, that here 9 data bits are used in- stead of 8 data bits in mode 0. 11 bits are transmitted (through sio_txd_o ) or received (through sio_rxd_i ): start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit ( tb8 in scon ) can be assigned the value of 0 or 1 . on receive, the 9th data bit goes into rb8 in special func- tion register scon , while the stop bit is ignored. in mode 2 the baud rate is programmable to either 1/32 or 1/64 of the clock input sio_clk_i . in mode 3 the baud rate is derived from the overflow rate of timer 1. [figure 13] shows a simplified function al diagram of the serial port in modes 2 and 3. the receive portion is exactly the same as in mode 1. the transmit portion differs from mode 1 only in the 9th bit of the transmit shift register. transmission is initiated by any instruction that uses sbuf as a destination register. transmission actually commences immediately after the next roll over in the divide-by-16 counter. (thus, the bit times are synchronized to the divide-by -16 counter, not to the ?write to sbuf ? signal.) after sending the start-bit and 9 data bits, the ti bit is set and the stop-bit is sent. reception is initiated by the detec tion of a 1-to-0 transition at sio_rxd_i . for this purpose sio_rxd_i is sampled at a rate of 16 times whatever baud rate has been established. when a transi- tion is detected, the divide-by-16 c ounter is immediately reset, thus it aligns its rollovers with the boundaries of the incoming bit times. at the 7th, 8t h, and 9th counter states of each bit time, the bit detector samples the value of sio_rxd_i . the value accepted is the value that was seen in at least 2 of the 3 samples. this is done for noise rejection. if the value accepted during the first bit time is not 0 , the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. this is to provide rejection of false start bits. after the 9 data bits and the stop-bit have been received, the result is loaded into sbuf and rb8 , and ri is set to 1 , but that is only done, if the following conditions are met: 1. ri = 0 , and 2. either sm2 = 0 , or the received stop bit = 1 . if either of these two conditions is not met, the received frame is irretrievably lost. if both conditions are met, the first 8 data bits go into sbuf , the 9 th data bit goes into rb8 , and ri is activated. then the unit goes back to looking for a 1-to-0 transition in sio_rxd_i .
HT80C51 user manual peripheral modules ? standard serial interface (sio0) handshake solutions ? philips electronics n.v. 2005 page 39 of 132 sbuf read only sbuf write only ht-sfr bus sio_rxd_i sio_txd _o ti >=1 ri >=1 int[4] sio _clk_i sio_active_o sio_clk_o send receive >=1 not send tb8 1/16 1 0 2 1 3 1/2 t1_overflow mode sio_mode0_o 0 0 rb8 bit sampler start-bit detector [figure 13] block diagram of serial interface in mode 1, 2, and 3 multiprocessor communications modes 2 and 3 have a special provision for multipro cessor communications. in these modes, 9 data bits are received. the 9th one goes into rb8 . then comes a stop bit. the port can be programmed such that when the stop bit is received, the se rial port interrupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon . a way to use this feature in multiprocessor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte that identifies the tar get slave. an address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. with sm2 = 1 , no slave will be in terrupted by a data byte. an address byte, however, will interrupt all slav es, so that each slave can examine the received byte and see if it is being address ed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that will be coming. the slaves that weren?t being addressed leave their sm2 s set and go on about their business, ignoring the coming data bytes. sm2 has no effect in mode 0, and in mode 1 it can be used to check the validity of the stop bit. in a mode 1 reception, if sm2 = 1 , the receive interrupt w ill not be activated unless a valid stop bit is re- ceived.
handshake solutions HT80C51 user manual peripheral modules ? standard serial interface (sio0) page 40 of 132 ? philips electronics n.v. 2005 5.3.5. setting up the serial port [table 8] summarizes the initialization values for scon to select different modes of the uart . baud rate scon sm0 sm1 sio mode smod = 0 smod = 1 sm2 = 0: single processor environment sm2 = 1: multi processor environment 0 0 1 1 0 1 0 1 mode 0: shift register mode 1: 8bit uart mode 2: 9bit uart mode 3: 9bit uart f sio_clk_i f t01_overflow /32 f sio_clk_i /64 f t01_overflow /32 f sio_clk_i f t01_overflow /16 f sio_clk_i /32 f t01_overflow /16 10h 50h 90h d0h na 70h b0h f0h [table 8] serial port setup 5.3.5.1. generating baud rates serial port in mode 0: mode 0 has a fixed baud rate which is the frequency at clock input sio_clk_i . to run the serial port in this mode none of the timer/counters need to be set up. only the scon register needs to be de- fined. i clk sio f rate baud _ _ = serial port in mode 1: mode 1 has a variable baud rate. timer 1 generates the baud rate. for this purpose, timer 1 is used in mode 2 (auto- reload). refer to the initialization section of the timer description (chapter 5.2.5). () [] 1 256 32 _ _ 01 th f k rate baud i clk t ? = if smod = 0 , then k = 1 . if smod = 1 , then k = 2 ( smod is in the pcon register). most of the time the user knows the baud rate and needs to know the reload value for th1 . ) ( 32 256 1 _ _ 01 rate baud f k th i clk t ? = th1 must be an integer value. rounding off th1 to the nearest integer may not produce the desired baud rate. in this case, the user may ha ve to choose another crystal frequency. since the pcon register is not bit addressable, one way to set the bit is logical oring the pcon register (i.e., orl pcon,#80h ). the address of pcon is 87h . serial port in mode 2: the baud rate is fixed in this mode and is 1/32 or 1/64 of the frequency at clock input sio_clk_i , depending on the value of the smod bit in the pcon register.
HT80C51 user manual peripheral modules ? standard serial interface (sio0) handshake solutions ? philips electronics n.v. 2005 page 41 of 132 in this mode none of the timers are used and t he clock comes from the serial clock input sio_clk_i . smod = 1 , baud rate = 1/32 of the frequency at sio_clk_i . smod = 0 , baud rate = 1/64 of the frequency at sio_clk_i . to set the smod bit: orl pcon,#80h. the address of pcon is 87h . serial port in mode 3: the baud rate in mode 3 is variable and sets up exactly the same as in mode 1.
handshake solutions HT80C51 user manual peripheral modules ? general purpose ios page 42 of 132 ? philips electronics n.v. 2005 5.4. general purpose ios this module comprises unidirectional, parallel input and/or output ports to read in signals from the environment or set signals for the system. 5.4.1. options the number and addresses of output ports c an be selected (ordered) by using options HT80C51_gpio_pout_count and HT80C51_gpio_pout_addresses . the number and addresses of input ports can be selected (ordered) by using options HT80C51_gpio_pin_count and HT80C51_gpio_pin_addresses . note: if an output port is placed at an address ending with 0h or 8h , the bits of the port are directly addressable. 5.4.2. special function registers (poutx pinx) pout0 output port 0 addr = 80h (configurable) reset value = ffh bits 7 6 5 4 3 2 1 0 pout0 bit symbol function pout0.7 .. pout0.0 set the output values of output pins gpio_pout0_o[7:0] pout1 output port 1 addr = 90h (configurable) reset value = ffh bits 7 6 5 4 3 2 1 0 pout1 bit symbol function pout1.7 .. pout1.0 set the output values of output pins gpio_pout1_o[7:0] pout2 output port 2 addr = a0h (configurable) reset value = ffh bits 7 6 5 4 3 2 1 0 pout2 bit symbol function pout2.7 .. pout2.0 set the output values of output pins gpio_pout2_o[7:0]
HT80C51 user manual peripheral modules ? general purpose ios handshake solutions ? philips electronics n.v. 2005 page 43 of 132 pout3 output port 3 addr = b0 (configurable) reset value = ffh bits 7 6 5 4 3 2 1 0 pout3 bit symbol function pout3.7 .. pout3.0 set the output values of output pins gpio_pout3_o[7:0] poutx output port x, x>3 addr = (configurable) reset value = ffh bits 7 6 5 4 3 2 1 0 poutx bit symbol function poutx.7 .. poutx.0 set the output values of output pins gpio_poutx_o[7:0] pinx input port x addr = (configurable) reset value = not applicable bits 7 6 5 4 3 2 1 0 pinx bit symbol function pinx.7 .. pinx.0 read the values of input pins gpio_pinx_o[7:0] . write accesses have no effect. 5.4.3. interrupts no interrupts are generated. 5.4.4. operation write accesses to output ports directly set the rela ted output pins. there is no synchronization to any external clocks done. read accesses to output por ts return the contents of the output latches. read accesses to input port return the values that are applied to their related input pins. write ac- cesses to an input port have no effect.
handshake solutions HT80C51 user manual peripheral modules ? i2c interface (sio1) page 44 of 132 ? philips electronics n.v. 2005 5.5. i 2 c interface (sio1) the handshake technology i2c (referred to as ht-i2c) is a low power version of the standard 80c51 i2c (as used in the 8xc552 80c51). the ht-i2c implementation offers several unique features, which are detailed below. ? the ht-i2c consumes almost zero stand-by pow er while in sleep mode, yet is immediately available for full-speed full-functional operation. ? the ht-i2c has very low electromagnetic emission (eme). ? the ht-i2c has low supply-current peaks, thus facilitating integration with analog and rf cir- cuitry. ? the ht-i2c use a dedicated special function register (ht-sfr) bus for interconnects with the HT80C51 micro-controller. 5.5.1. options a master-slave combination of the i2 c interface can be ordered by option HT80C51_i2c . a slave-only i2c interface can be ordered by using option HT80C51_i2c_slaveonly . 5.5.2. special function registers (s1con s1adr s1dat s1sta ) s1con sio1 control register addr = d8h reset value = 00h bits 7 6 5 4 3 2 1 0 cr2 ens1 sta sto si aa cr1 cr0 bit symbol function s1con.7 cr2 clock rate bit 2 (not implemented in slave-only version) s1con.6 ens1 1: 0: sio1 enable bit sio1 enabled sio1 disabled s1con.5 sta start flag, starts transmissi on (not implemented in slave-only version) s1con.4 sto stop flag, stops transmission s1con.3 si serial interrupt; set by hardware, when an interrupt request is gener- ated; must be reset be software s1con.2 aa 1: 0: assert acknowledge flag; type of acknowledge to be returned return not ack return ack s1con.1 cr1 clock rate bit 1 (not implemented in slave-only version) s1con.0 cr0 clock rate bit 0 (not implemented in slave-only version) note: for ?not implemented? bits always write 0s, read accesses always return 0. the master and slave operate on a common clock signal, which depends on the actual values of the signals cr0 , cr1 and cr2 . changing one or more of the following bits cr0 , cr1 or cr2 during a data transfer may lead to unpredictable results. the baud ra tes are derived from a dedicated clock input pin ( i2c_clk_i ). note: baud rate generation and clock input pin ( i2c_clk_i ) are not available for the slave-only ver- sion.
HT80C51 user manual peripheral modules ? i2c interface (sio1) handshake solutions ? philips electronics n.v. 2005 page 45 of 132 cr2 cr1 cr0 baud rate 0 0 0 f i2c_clk_i /256 0 0 1 f i2c_clk_i /224 0 1 0 f i2c_clk_i /192 0 1 1 f i2c_clk_i /160 1 0 0 f i2c_clk_i /960 1 0 1 f i2c_clk_i /120 1 1 0 f i2c_clk_i /60 1 1 1 timer 1 overflow rate / 8 s1adr sio1 slave address register addr = dbh reset value = 00h bits 7 6 5 4 3 2 1 0 slave address gc bit symbol function s1adr.7 s1adr.6 s1adr.5 s1adr.4 s1adr.3 s1adr.2 s1adr.1 own slave address in slave mode. s1adr.0 gc 1: 0: general call enable general call address is recognized. general call address is not recognized. s1dat sio1 data register addr = dah reset value = 00h bits 7 6 5 4 3 2 1 0 transmit / receive data bit symbol function s1dat.7 s1dat.6 s1dat.5 s1dat.4 s1dat.3 s1dat.2 s1dat.1 s1dat.0 data byte to be transmitted or been received. s1dat remains un- changed by hardware, as long as si (in s1con ) is set.
handshake solutions HT80C51 user manual peripheral modules ? i2c interface (sio1) page 46 of 132 ? philips electronics n.v. 2005 s1sta sio1 status register addr = d9h reset value = f8h bits 7 6 5 4 3 2 1 0 status 0 0 0 bit symbol function s1sta.7 s1sta.6 s1sta.5 s1sta.4 s1sta.3 status code. the status is valid as long as si is set. when no relevant status is available, s1sta contains the value f8h . s1sta.2 s1sta.1 s1sta.0 always 0 . 5.5.3. interrupts the ht-i2c can generate only one interrupt. if the bit si in the sfr s1con is set, an interrupt is re- quested on line int_req_i[5] . si is set by hardware but has to be cleared by software, for instance in the interrupt service routine. 5.5.4. operation the i2c bus uses two wires (sda and scl) to transfer information between devices connected to the bus. the main features of the bus are: ? bidirectional data transfer between masters and slaves ? multimaster bus (no central master) ? arbitration between simultaneously transmitting mast ers without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer ? the i2c bus may be used for test and diagnostic purposes the ht-i2c logic (here also named sio1) provides a serial interface that me ets the i2c bus specifica- tion and supports all transfer modes (other than the low-speed mode) from and to the i2c bus. the ht-i2c logic handles bytes transfer autonomously. it also keeps track of serial transfers, and a status register ( s1sta ) reflects the status of ht-i2c and the i2c bus. the cpu interfaces to the i2c logic via the following four special function registers: s1con (sio1 con- trol register), s1sta (sio1 status register), s1dat (sio1 data register), and s1adr (sio1 slave address register). the sio1 logic interfaces to the external i2c bus via two port 1 pins: scl (serial clock line) and sda (serial data line). a typical i2c bus configuration is shown in [figur e 14]. [figure 15] shows how a data transfer is ac- complished on the bus. depending on the state of the direction bit (r /w), two types of data transfers are possible on the i2c bus: 1. data transfer from a master transmitter to a slave receiver. t he first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an ac- knowledge bit after each received byte.
HT80C51 user manual peripheral modules ? i2c interface (sio1) handshake solutions ? philips electronics n.v. 2005 page 47 of 132 2. data transfer from a slave transmitter to a mast er receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. next follows the data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all re- ceived bytes other than the last byte. at the end of the last received byte, a ?not acknowledge? is returned. the master device generates all of the serial cl ock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next se rial transfer, the i2c bus will not be released. 5.5.4.1. modes of operation the on-chip sio1 logic may operate in the following four modes: 1. master transmitter mode (not available for slave-only version) serial data output through sda while scl outputs the serial clock. the first transmitted byte contains the slave address of the receiving device (7 bits) and the data direction bit. in this mode the data direc- tion bit (r/w) will be logic 0, and we say that a ?w? is transmitted. thus the first byte transmitted is sla+w. serial data is transmitted 8 bits at a time. after ea ch byte is transmitted, an acknowledge bit is re- ceived. start and stop conditions are output to indicate the beginning and the end of a serial transfer. 2. master receiver mode (not available for slave-only version) the first transmitted byte contains the slave address of the transm itting device (7 bits) and the data direction bit. in this mode the data direction bit (r /w) will be logic 1, and we say that an ?r? is transmit- ted. thus the first byte transmitted is sla+r. serial data is received via sda while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are output to indicate the beginning and end of a serial transfer. 3. slave receiver mode: serial data and the serial clock are received throug h sda and scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is pe rformed by hardware after reception of the slave address and direction bit. 4. slave transmitter mode: the first byte is received and handled as in the sl ave receiver mode. however, in this mode, the di- rection bit will indicate that the transfer direction is reversed. serial data is transmitted via sda while the serial clock is input through scl. start an d stop conditions are recognized as the beginning and end of a serial transfer. in a given application, sio1 may operate as a mast er and as a slave. in the slave mode, the sio1 hardware looks for its own slave address and the gener al call address. if one of these addresses is detected, an interrupt is requested. when the microc ontroller wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. if bus arbitration is lost in th e master mode, sio1 switches to the slave mode im- mediately and can detect its own slave address in the same serial transfer.
handshake solutions HT80C51 user manual peripheral modules ? i2c interface (sio1) page 48 of 132 ? philips electronics n.v. 2005 other device with i 2 c interface other device with i 2 c interface p89c66x p1.7/sda p1.6/scl sda scl rp rp v dd i 2 c bus [figure 14] typical i 2 c bus configuration 12 78 ack 9123-8 ack 9 repeated if more bytes are transferred clock line held low while interrupts are serviced acknowledgment signal from receiver acknowledgment signal from receiver r/w direction bit slave address msb sda scl stop condition repeated start condition p/s s start condition [figure 15] data transfer on the i 2 c bus 5.5.4.2. sio1 implementation and operation [figure 16] shows how the on-chip i2c bus interface is implemented, and the following text describes the individual blocks. input filters and output stages the input filters should have i2c compatible input levels. if the input voltage is less than 1.5 v, the input logic level is interpreted as 0; if the input voltage is greater than 3.0 v, the input logic level is interpreted as 1. for low speed implementations it is advisable to use input filter circuits for the pins sda and scl, to suppress noise on these signals.
HT80C51 user manual peripheral modules ? i2c interface (sio1) handshake solutions ? philips electronics n.v. 2005 page 49 of 132 the output stages should consist of open drain transisto rs that can sink 3ma at vout < 0.4 v. these open drain outputs should not have clamping diodes to vdd. thus, if the device is connected to the i2c bus and vdd is switched off, the i2c bus is not affected. address register, s1adr this 8-bit special function register may be loaded wi th the 7-bit slave address (7 most significant bits) to which sio1 will respond when programmed as a sl ave transmitter or rece iver. the lsb (gc) is used to enable general call address ( 00h ) recognition. comparator the comparator compares the received 7-bit slave ad dress with its own slave address (7 most signifi- cant bits in s1adr ). it also compares the first received 8-bit byte with the general call address ( 00h ). if equality is found, the appropriate status bits are set and an interrupt is requested. shift register, s1dat this 8-bit special function register contains a byte of serial data to be transmitted or a byte, which has just been received. data in s1dat is always shifted from right to left; the first bit to be transmitted is the msb (bit 7) and, after a byte has been received, the first bit of received data is located at the msb of s1dat . while data is being shifted out, data on the bus is simultaneously being shifted in; s1dat al- ways contains the last byte present on the bus. thus, in the event of lost arbitration, the transiti on from master transmitter to slave receiver is made with the correct data in s1dat .
handshake solutions HT80C51 user manual peripheral modules ? i2c interface (sio1) page 50 of 132 ? philips electronics n.v. 2005 address register comparator shift register control register status register status decoder serial clock generator timing & control logic arbitration & sync logic input filter output stage input filter output stage ack 8 8 8 8 internal bus s1adr s1dat s1con s1sta sda scl i2c_sda_i i2c_sda_o i2c_scl_i i2c_scl_o i2c_clk_i interrupt t1_overflow status bits HT80C51 external pad drivers [figure 16] i 2 c bus serial interface block diagram
HT80C51 user manual peripheral modules ? i2c interface (sio1) handshake solutions ? philips electronics n.v. 2005 page 51 of 132 arbitration and synchronization logic in the master transmitter mode, the arbitration l ogic checks that every transmitted logic 1 actually appears as a logic 1 on the i2c bus. if another devic e on the bus overrules a logic 1 and pulls the sda line low, arbitration is lost, and sio1 immediately changes from master transmitter to slave receiver. sio1 will continue to output clock pulses (on scl) unt il transmission of the curre nt serial byte is com- plete. arbitration may also be lost in the master receiver mode. loss of arbitration in this mode can only occur while sio1 is returning a ?not acknowledge: (log ic 1) to the bus. arbitration is lost when another device on the bus pulls this signal low. since this can occur only at the end of a serial byte, sio1 generates no further clock pulses. the arbitration procedure is illustrated in [figure 17]. the synchronization logic will synchronize the serial clock generator with the clock pulses on the scl line from another device. if two or more master dev ices generate clock pulses, the ?mark? duration is determined by the device that generates the shortest ?marks,? and the ?space? duration is determined by the device that generates the longest ?spaces.? [figure 18] shows the synchronization procedure. a slave may stretch the space duration to slow dow n the bus master. the space duration may also be stretched for handshaking purposes. this can be done after each bit or after a complete byte transfer. sio1 will stretch the scl space duration after a byte has been transmitted or received and the ac- knowledge bit has been transferred. the serial interrupt flag ( si ) is set, and the stretching continues until the serial interrupt flag is cleared. 1234 89 ack scl sda (3) (2) (1) (1) (1) another device transmits identical serial data . (2) another device overrules a logic 1 (dotted line) transmitted by sio1 (master) by pulling the sda line low. arbitration is lost, and sio1 enters the slave receiver mode. (3) sio1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted . sio1 will not generate clock pulses for the next byte. data on sda originates from the new master once it has won arbitration . [figure 17] arbitration procedure
handshake solutions HT80C51 user manual peripheral modules ? i2c interface (sio1) page 52 of 132 ? philips electronics n.v. 2005 sda scl space duration (2) mark duration (1) (3) (1) (1) another service pulls the scl line low before the sio 1 "mark" duration is complete. the serial clock generator is immediately reset and commences with the "space" duration by pulling scl low . (2) another device still pulls the scl line low after sio 1 releases scl. the serial clock generator is forced into the wait state until the scl line is released . (3) the scl line is released, and the serial clock generator commences with the mark duration . [figure 18] serial clock synchronization serial clock generator this programmable clock pulse generator provides t he scl clock pulses when sio1 is in the master transmitter or master receiver mode. it is switch ed off when sio1 is in a slave mode. the program- mable output clock frequencies are: f i2c_clk_i /60 to f i2c_clk_i /256 and the timer 1 overflow rate divided by eight. the output clock pulses have a 50% duty cycle unless the clock generator is synchronized with other scl clock sources as described above. timing and control the timing and control logic generates the timing and control signals for serial byte handling. this logic block provides the shift pulses for s1dat , enables the comparator, generates and detects start and stop conditions, receives and transmits acknowledge bits, controls the master and slave modes, con- tains interrupt request logic, and monitors the i2c bus status. control register, s1con this 7-bit special function register is used by t he microcontroller to control the following sio1 func- tions: start and restart of a serial transfer, terminat ion of a serial transfer, bit rate, address recognition, and acknowledgment. status decoder and status register the status decoder takes all of the internal status bits and compresses them into a 5-bit code. this code is unique for each i2c bus status. the 5-bit code may be used to generate vector addresses for fast processing of the various service routines. each service routine processes a particular bus status. there are 26 possible bus states if all four modes of sio1 are used. the 5-bit status code is latched
HT80C51 user manual peripheral modules ? i2c interface (sio1) handshake solutions ? philips electronics n.v. 2005 page 53 of 132 into the five most significant bits of the status register when the se rial interrupt flag is set (by hard- ware) and remains stable until the interrupt flag is clear ed by software. the three least significant bits of the status register are always zero. if the status code is used as a vector to service routines, then the routines are displaced by eight address locations. eight bytes of code are sufficient for most of the service routines. 5.5.4.3. the four sio1 special function registers the microcontroller interfaces to sio1 via four special function registers. these four sfrs ( s1adr , s1dat , s1con , and s1sta ) are described individually in the following sections. the address register, s1adr the cpu can read from and write to this 8-bit, directly addressable sfr. s1adr is not affected by the sio1 hardware. the contents of this register are irrelevant when si o1 is in a master mode. in the slave modes, the seven most significant bits must be loaded with the microcontroller?s own slave ad- dress, and, if the least significant bit is set, the general call address ( 00h ) is recognized; otherwise it is ignored. 7 6 5 4 3 2 1 0 s1adr (dbh) own slave address gc the most significant bit corresponds to the first bit received from the i2c bus after a start condition. a logic 1 in s1adr corresponds to a high level on the i2c bus, and a logic 0 corresponds to a low level on the bus. the data register, s1dat s1dat contains a byte of serial data to be transmi tted or a byte, which has just been received. the cpu can read from and write to this 8-bit, directly addressable sfr while it is not in the process of shifting a byte. this occurs when sio1 is in a defined state and the serial interrupt flag is set. data in s1dat remains stable as long as si is set. data in s1dat is always shifted from right to left: the first bit to be transmitted is the msb (bit 7), and, after a byte has been rece ived, the first bit of received data is located at the msb of s1dat . while data is being shifted out, data on the bus is simultaneously being shifted in; s1dat always contains the last dat a byte present on the bus. thus, in the event of lost arbi- tration, the transition from master transmitter to slave receiver is made with the correct data in s1dat . 7 6 5 4 3 2 1 0 s1dat (dah) sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 shift direction sd7 - sd0: eight bits to be transmitted or just received. a logic 1 in s1dat corresponds to a high level on the i2c bus, and a logic 0 corresponds to a low level on the bus. serial data shifts through s1dat from right to left. [figure 19] shows how data in s1dat is serially transferred to and from the sda line. s1dat and the ack flag form a 9-bit shift register which shifts in or shifts out an 8-bit byte, followed by an acknowledge bit. the ack flag is controlled by the sio1 hardware and cannot be accessed by the cpu. serial data is shifted through the ack flag into s1dat on the rising edges of serial clock pulses
handshake solutions HT80C51 user manual peripheral modules ? i2c interface (sio1) page 54 of 132 ? philips electronics n.v. 2005 on the scl line. when a byte has been shifted into s1dat , the serial data is available in s1dat , and the acknowledge bit is returned by the control logic during the ninth clock pulse. serial data is shifted out from s1dat via a buffer ( bsd7 ) on the falling edges of clock pulses on the scl line. when the cpu writes to s1dat , bsd7 is loaded with the content of s1dat.7 , which is the first bit to be transmitted to the sda line (see [figure 20]). afte r nine serial clock pulses, the eight bits in s1dat will have been transmitted to the sda line, and the acknowledge bit will be present in ack . note that the eight transmitted bits are shifted back into s1dat . the control register, s1con the cpu can read from and write to this 8-bit, dire ctly addressable sfr. two bi ts are affected by the sio1 hardware: the si bit is set when a serial interrupt is requested, and the sto bit is cleared when a stop condition is present on the i2c bus. the sto bit is also cleared when ens1 = ? 0 ?. 7 6 5 4 3 2 1 0 s1con (d8h) cr2 ens1 sta sto si aa cr1 cr0 ens1, the sio1 enable bit: ens1 = ? 0 ?: when ens1 is ? 0 ?, the sda and scl outputs are in a high impedance state. sda and scl input signals are ignored, sio1 is in the ?not addressed? slave state, and the sto bit in s1con is forced to ? 0 ?. no other bits are affected. ens1 = ? 1 ?: when ens1 is ? 1 ?, sio1 is enabled. ens1 should not be used to temporarily releas e sio1 from the i2c bus since, when ens1 is reset, the i2c bus status is lost. the aa flag should be used instead (see description of the aa flag in the follow- ing text). internal bus 8 s1dat ack bsd7 sda scl shift pulses [figure 19] serial input/output configuration
HT80C51 user manual peripheral modules ? i2c interface (sio1) handshake solutions ? philips electronics n.v. 2005 page 55 of 132 d7 d6 d5 d4 d3 d2 d1 d0 a sda scl (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) d7 d6 d5 d4 d3 d2 d1 d0 (3) a (1) (1) shift ack & s1dat ack s1dat shift bsd7 bsd7 loaded by the cpu shift in shift out (1) valid data in s1dat (2) shifting data in s1dat and ack (3) high level on sda [figure 20] shift-in and shift-out timing in the following text, it is assumed that ens1 = ? 1 ?. the ?start? flag, sta sta = ? 1 ?: when the sta bit is set to enter a master mode, the sio1 hardware checks the status of the i2c bus and generates a start condition if the bus is free. if the bus is not free, then sio1 waits for a stop conditi on (which will free the bus) and generates a start condition after a delay of half a clock period of the internal serial clock genera- tor. if sta is set while sio1 is already in a master mode and one or more bytes are trans- mitted or received, sio1 transm its a repeated start condition. sta may be set at any time. sta may also be set when sio1 is an addressed slave. sta = ? 0 ?: when the sta bit is reset, no start condition or repeated start condition will be generated. the stop flag, sto sto = ? 1 ?: when the sto bit is set while sio1 is in a master mode, a stop condition is transmit- ted to the i2c bus. when the stop condi tion is detected on the bus, the sio1 hard- ware clears the sto flag. in a slave mode, the sto flag may be set to recover from an error condition. in this case, no stop condition is transmitted to the i2c bus. how- ever, the sio1 hardware behaves as if a stop condition has been received and
handshake solutions HT80C51 user manual peripheral modules ? i2c interface (sio1) page 56 of 132 ? philips electronics n.v. 2005 switches to the defined ?not addressed? slave receiver mode. the sto flag is auto- matically cleared by hardware. if the sta and sto bits are both set, the a stop condition is transmitted to the i2c bus if sio1 is in a master mode (in a slave mode, sio1 generates an internal stop condition which is not transmitted). sio1 then transmits a start condition. sto = ? 0 ?: when the sto bit is reset, no stop condition will be generated. the serial interrupt flag, si si = ? 1 ?: when the si flag is set, then, if the ea and es1 (interrupt enable regi ster) bits are also set, a serial interrupt is requested. si is set by hardware when one of 25 of the 26 possible sio1 states is entered. the only state that does not cause si to be set is state f8h, which indicates that no rele vant state information is available. while si is set, the low period of the serial clock on the scl line is stretched, and the serial transfer is suspended. a high level on the scl line is unaffected by the serial in- terrupt flag. si must be reset by software. si = ? 0 ?: when the si flag is reset, no serial interrupt is requested, and there is no stretching of the serial clock on the scl line. the assert acknowledge flag, aa aa = ? 1 ?: if the aa flag is set, an acknowledge (low le vel to sda) will be returned during the acknowledge clock pulse on the scl line when: - the ?own slave address? has been received - the general call address has been received while the general call bit ( gc ) in s1adr is set - a data byte has been received while sio1 is in the master receiver mode - a data byte has been received while sio1 is in the addressed slave receiver mode aa = ? 0 ?: if the aa flag is reset, a not acknowled ge (high level to sda) will be returned during the acknowledge clock pulse on scl when: - a data has been received while sio1 is in the master receiver mode - a data byte has been received while sio1 is in the addressed slave receiver mode when sio1 is in the addre ssed slave transmitter mode, state c8h w ill be entered after the last serial is transmitted (see [figure 11]). when si is cleared, sio1 leaves st ate c8h, enters the not address ed slave receiver mode, and the sda line remains at a high level. in state c8h, the aa flag can be set again for future address recogni- tion. when sio1 is in the not addressed slave mode, its own slave address and the general call address are ignored. consequently, no acknowledge is returned, and a serial interrupt is not requested. thus, sio1 can be temporarily released from the i2c bus wh ile the bus status is monitored. while sio1 is released from the bus, start and stop conditions are detected, and serial data is shifted in. ad- dress recognition can be resumed at any time by setting the aa flag. if the aa flag is set when the part?s own slave address or the general call ad dress has been partly received, the address will be recognized at the end of the byte transmission.
HT80C51 user manual peripheral modules ? i2c interface (sio1) handshake solutions ? philips electronics n.v. 2005 page 57 of 132 the clock rate bits cr0, cr1, and cr2 these three bits determine the serial clock fre quency when sio1 is in a master mode. the various serial rates are shown in [table 9]. a 12.5 khz bit rate may be used by devices that in terface to the i2c bus via standard i/o port lines which are software driven and slow. 100 khz is usually the maximum bit rate and can be derived from a 16 mhz, 12 mhz, or a 6 mhz oscilla tor. a variable bit rate (0.5 khz to 62.5 khz) may also be used if timer 1 is not required for any other purpose while sio1 is in a master mode. the frequencies shown in [table 9] are unimportant when sio1 is in a slave mode. in the slave modes, sio1 will automatically synchronize with any clock frequency up to 100 khz. the status register, s1sta s1sta is an 8-bit read-only special function register. t he three least significant bits are always zero. the five most significant bits contain the status code. there are 26 possible status codes. when s1sta contains f8h, no relevant state in formation is available and no serial interrupt is requested. all other s1sta values correspond to defined sio1 states. when ea ch of these states is entered, a serial inter- rupt is requested ( si = ? 1 ?). a valid status code is present in s1sta one machine cycle after si is set by hardware and is still present one machine cycle after si has been reset by software. bit rate (kbit/s) at f iclk cr2 cr1 cr0 6 mhz 12 mhz 16 mhz 24 mhz 30 mhz f iclk divided by 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 23 27 31 37 6.25 50 100 0.24..62.5 0..255 47 54 63 75 12.5 100 200 0.49..62.5 0..254 62.5 71 83.3 100 17 133 267 0.65..55.6 0..253 94 107 125 150 25 200 400 0.98..50.0 0..251 117 134 155 188 31 250 500 1.22..52.1 0..250 256 224 192 160 960 120 60 256-(reload value timer 1) reload value timer 1, mode 2 [table 9] serial clock rates (needs update) notes: 1. these frequencies exceed the upper limit of 100 khz of the i2 c-bus specification and cannot be used in an i2c-bus application. 2. at fosc = 24 mhz/30 mhz the maximum i2c bus rate of 100 khz cannot be realized due to the fixed divider rates. 5.5.4.4. more information on sio1 operating modes the four operating modes are: ? master transmitter ? master receiver ? slave receiver ? slave transmitter data transfers in each mode of operation are shown in [figure 21] to [figure 24].
handshake solutions HT80C51 user manual peripheral modules ? i2c interface (sio1) page 58 of 132 ? philips electronics n.v. 2005 these figures contain the following abbreviations: abbreviation explanation s start condition sla 7-bit slave address r read bit (high level at sda) w write bit (low level at sda) a acknowledge bit (low level at sda) a not acknowledge bit (high level at sda) data 8-bit data byte p stop condition in [figure 21] to [figure 24], circles are used to indicate when the serial interrupt flag is set. the num- bers in the circles show t he status code held in the s1sta register. at these poi nts, a service routine must be executed to continue or complete the serial transfer. these service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. when a serial interrupt routine is entered, the status code in s1sta is used to branch to the appropri- ate service routine. for each st atus code, the required software ac tion and details of the following serial transfer are given in [table 10] to [table 14]. master transmitter mode (not available for slave-only version) in the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see [figure 21]). before the master transmitter mode can be entered, s1con must be initialized as follows: 7 6 5 4 3 2 1 0 s1con (d8h) cr2 ens1 sta sto si aa cr1 cr0 bit rate 1 0 0 0 x bit rate cr0 , cr1 , and cr2 define the serial bit rate. ens1 must be set to logic 1 to enable sio1. if the aa bit is reset, sio1 will not acknowledge its own slave addr ess or the general call a ddress in the event of another device becoming master of the bus. in other words, if aa is reset, sio0 cannot enter a slave mode. sta , sto , and si must be reset. the master transmitter mode may now be entered by setting the sta bit using the setb instruction. the sio1 logic will now test the i2c bus and generat e a start condition as soon as the bus becomes free. when a start condition is transmitted, the serial interrupt flag ( si ) is set, and the status code in the status register ( s1sta ) will be 08h . this status code must be used to vector to an interrupt service routine that loads s1dat with the slave address and the data direction bit ( sla+w ). the si bit in s1con must then be reset before the se rial transfer can continue. when the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag ( si ) is set again, and a number of status codes in s1sta are possible. there are 18h , 20h , or 38h for the master mode and also 68h , 78h , or b0h if the slave mode was enabled ( aa = logic 1). the appropriate action to be ta ken for each of these status codes is detailed in [table 10]. after a repeated start condition (state 10h ). sio1 may switch to the master re- ceiver mode by loading s1dat with sla+r ).
HT80C51 user manual peripheral modules ? i2c interface (sio1) handshake solutions ? philips electronics n.v. 2005 page 59 of 132 master receiver mode (not available for slave-only version) in the master receiver mode, a number of data bytes are received from a slave transmitter (see [figure 22]). the transfer is initialized as in the master transmitter mode. when the start condition has been transmitted, the interrupt service routine must load s1dat with the 7-bit slave address and the data direction bit ( sla+r ). the si bit in s1con must then be cleared before th e serial transfer can con- tinue. when the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag ( si ) is set again, and a number of status codes in s1sta are possible. these are 40h , 48h , or 38h for the master mode and also 68h , 78h , or b0h if the slave mode was enabled ( aa = logic 1). the appropriate action to be ta ken for each of these status codes is detailed in [table 11]. ens1 , cr1 , and cr0 are not affected by the serial transfer and are not referred to in table 5. after a repeated start condition (state 10h ), sio1 may switch to the master transmitter mode by loading s1dat with sla+w . slave receiver mode in the slave receiver mode, a number of data bytes are received from a master transmitter (see [figure 23]). to initiate the slave receiver mode, s1adr and s1con must be loaded as follows: 7 6 5 4 3 2 1 0 s1adr (dbh) own slave address gc the upper 7 bits are the address to which sio1 will respond when addressed by a master. if the lsb ( gc ) is set, sio1 will respond to the general call address ( 00h ); otherwise it ignores the general call address. 7 6 5 4 3 2 1 0 s1con (d8h) cr2 ens1 sta sto si aa cr1 cr0 x 1 0 0 0 1 x x cr0 , cr1 , and cr2 do not affect sio1 in the slave mode. ens1 must be set to logic 1 to enable sio1. the aa bit must be set to enable sio1 to acknowled ge its own slave address or the general call ad- dress. sta , sto , and si must be reset. when s1adr and s1con have been initialized, sio1 waits until it is addressed by its own slave ad- dress followed by the data direction bit which must be ? 0 ? ( w ) for sio1 to operate in the slave re- ceiver mode. after its ow n slave address and the w bit have been received, the serial interrupt flag (i) is set and a valid status code can be read from s1sta . this status code is used to vector to an inter- rupt service routine, and the appropriate action to be taken for each of these status codes is detailed in [table 12]. the slave receiver mode may also be ent ered if arbitration is lost while sio1 is in the master mode (see status 68h and 78h ). if the aa bit is reset during a transfer, sio1 will retu rn a not acknowledge (logic 1) to sda after the next received data byte. while aa is reset, sio1 does not respond to its own slave address or a gen- eral call address. however, the i2c bus is still monitored and address recognition may be resumed at any time by setting aa . this means that the aa bit may be used to temporarily isolate sio1 from the i2c bus.
handshake solutions HT80C51 user manual peripheral modules ? i2c interface (sio1) page 60 of 132 ? philips electronics n.v. 2005 slave transmitter mode in the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see [figure 24]). data transfer is initializ ed as in the slave receiver mode. when s1adr and s1con have been initialized, sio1 waits until it is addressed by its own slave addr ess followed by the data direction bit which must be ? 1 ? ( r ) for sio1 to operate in the slave transmitter mode. after its own slave ad- dress and the r bit have been received, the serial interrupt flag ( si ) is set and a valid status code can be read from s1sta . this status code is used to vector to an interrupt service routine, and the appro- priate action to be taken for each of these status codes is detailed in [table 12]. the slave transmitter mode may also be entered if arbitration is lost while sio1 is in the master mode (see state b0h ). if the aa bit is reset during a transfer, sio1 will transm it the last byte of t he transfer and enter state c0h or c8h . sio1 is switched to the ?not addressed? slav e mode and will ignore the master receiver if it continues the transfer. thus the master rece iver receives all 1s as serial data. while aa is reset, sio1 does not respond to its own slave address or a general call address. however, the i2c bus is still monitored, and address recognition may be resumed at any time by setting aa . this means that the aa bit may be used to temporarily isolate sio1 from the i2c bus.
HT80C51 user manual peripheral modules ? i2c interface (sio1) handshake solutions ? philips electronics n.v. 2005 page 61 of 132 s sla w a a data p s sla w r 28h 18h 08h 10h successful transmission to a slave receiver next transfer started with a repeated start condition a p 20h not acknowledge received after the slave address 68h other mst continues a 78h 80h to corresponding states in slave mode to mst/rec mode entry=mr a data n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus: see table 4 mt a p 30h not acknowledge received after a data byte a or a 38h other mst continues a or a 38h other mst continues arbitration lost in slave address or data byte arbitration lost and addre ssed as slave [figure 21] format and states in the master transmitter mode
handshake solutions HT80C51 user manual peripheral modules ? i2c interface (sio1) page 62 of 132 ? philips electronics n.v. 2005 a or a s sla r a a data data a p s sla r w 58h 50h 40h 08h 10h successful reception from a slave transmitter next transfer started with a repeated start condition a p 48h not acknowledge received after the slave address 38h arbitration lost in slave address or acknowledge bit other mst continues 38h other mst continues a 68h other mst continues a 78h 80h arbitration lost and addressed as slave to corresponding states in slave mode to mst/trx mode entry=mt a data n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus: see table 5 mr [figure 22] format and states in the master receiver mode
HT80C51 user manual peripheral modules ? i2c interface (sio1) handshake solutions ? philips electronics n.v. 2005 page 63 of 132 s sla w a a data data 80h 60h reception of the own slave address and one or more data bytes all are acknowledged last data byte received is not acknowledged a 68h arbitration lost as mst and addressed as slave a data n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus: see table 6 reception of the general call address and one or more data bytes last data byte is not acknowledged arbitration lost as mst and addressed as slave by general call a p or s 80h a0h a p or s 88h general call a a data data 90h 70h a p or s 90h a0h a p or s 98h 78h a [figure 23] format and states in the slave receiver mode
handshake solutions HT80C51 user manual peripheral modules ? i2c interface (sio1) page 64 of 132 ? philips electronics n.v. 2005 s sla r a a data data b8h a8h reception of the own slave address and one or more data bytes all are acknowledged a data n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus: see table 7 p or s c0 h a a b0h a c8h p or s all "1"s arbitration lost as mst and addressed as slave last data byte transmitted . switched to not addressed slave (aa bit in s1con= "0") [figure 24] format and states of the slave transmitter mode
HT80C51 user manual peripheral modules ? i2c interface (sio1) handshake solutions ? philips electronics n.v. 2005 page 65 of 132 application software response to s1con status code s1sta status of the i2c bus and sio1 hardware to/from s1dat sta sto si aa next action taken by sio1 hard- ware 08h a start condition has been transmitted load sla+w x 0 0 x sla+w will be transmitted; ack bit will be received 10h a repeated start condition has been transmitted load sla+w or load sla+r x x 0 0 0 0 x x as above sla+w will be transmitted; sio1 will be switched to mst/rec mode 18h sla+w has been transmit- ted; ack has been received load data byte or no s1dat action or no s1dat action or no s1dat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted; ack bit will be received repeated start will be transmitted; stop condition will be transmitted; sto flag will be reset stop condition followed by a start condition will be transmitted; sto flag will be reset 20h sla+w has been transmit- ted; not ack has been received load data byte or no s1dat action or no s1dat action or no s1dat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted; ack bit will be received repeated start will be transmitted; stop condition will be transmitted; sto flag will be reset stop condition followed by a start condition will be transmitted; sto flag will be reset 28h data byte in s1dat has been transmitted; ack has been received load data byte or no s1dat action or no s1dat action or no s1dat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted; ack bit will be received repeated start will be transmitted; stop condition will be transmitted; sto flag will be reset stop condition followed by a start condition will be transmitted; sto flag will be reset 30h data byte in s1dat has been transmitted; not ack has been received load data byte or no s1dat action or no s1dat action or no s1dat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted; ack bit will be received repeated start will be transmitted; stop condition will be transmitted; sto flag will be reset stop condition followed by a start condition will be transmitted; sto flag will be reset 38h arbitration lost in sla+r/w or data bytes no s1dat action or no s1dat action 0 1 0 0 0 0 x x i2c bus will be released; not addressed slave will be entered a start condition will be transmitted when the bus becomes free [table 10] master transmitter mode (not available for slave-only version)
handshake solutions HT80C51 user manual peripheral modules ? i2c interface (sio1) page 66 of 132 ? philips electronics n.v. 2005 application software response to s1con status code s1sta status of the i2c bus and sio1 hardware to/from s1dat sta sto si aa next action taken by sio1 hard- ware 08h a start condition has been transmitted load sla+r x 0 0 x sla+w will be transmitted; ack bit will be received 10h a repeated start condition has been transmitted load sla+r or load sla+w x x 0 0 0 0 x x as above sla+w will be transmitted; sio1 will be switched to mst/trx mode 38h arbitration lost in not ack bit no s1dat action or no s1dat action 0 1 0 0 0 0 x x i2c bus will be released; sio1 will enter slave mode a start condition will be transmitted when the bus becomes free 40h sla+r has been transmitted; ack has been received no s1dat action or no s1dat action 0 0 0 0 0 0 0 1 data byte will be received; not ack bit will be returned data byte will be received; ack bit will be returned 48h sla+r has been transmitted; not ack has been received no s1dat action or no s1dat action or no s1dat action 1 0 1 0 1 1 0 0 0 x x x repeated start will be transmitted stop condition will be transmitted; sto flag will be reset stop condition followed by a start condition will be transmitted; sto flag will be reset 50h data byte has been received; ack has been returned read data byte or read data byte 0 0 0 0 0 0 0 1 data byte will be received; not ack bit will be returned data byte will be received; ack bit will be returned 58h data byte has been received; not ack has been returned read data byte or read data byte or read data byte 1 0 1 0 1 1 0 0 0 x x x repeated start will be transmitted stop condition will be transmitted; sto flag will be reset stop condition followed by a start condition will be transmitted; sto flag will be reset [table 11] master receiver mode (not available for slave-only version)
HT80C51 user manual peripheral modules ? i2c interface (sio1) handshake solutions ? philips electronics n.v. 2005 page 67 of 132 application software response to s1con status code s1sta status of the i2c bus and sio1 hardware to/from s1dat sta sto si aa next action taken by sio1 hardware 60h own sla+w has been received; ack has been returned no s1dat action or no s1dat action x x 0 0 0 0 0 1 data byte will be received; not ack bit will be returned data byte will be received; ack bit will be returned 68h arbitration lost in sla+r/w as master; own sla+w has has been received; ack has been returned no s1dat action or no s1dat action x x 0 0 0 0 0 1 data byte will be received; not ack bit will be returned data byte will be received; ack bit will be returned 70h general call address (00h) has been received; ack has been returned no s1dat action or no s1dat action x x 0 0 0 0 0 1 data byte will be received; not ack bit will be returned data byte will be received; ack bit will be returned 78h arbitration lost in sla+r/w as master; general call address (00h) has been received; ack has been returned no s1dat action or no s1dat action x x 0 0 0 0 0 1 data byte will be received; not ack bit will be returned data byte will be received; ack bit will be returned 80h previously addressed with own slv address; data has been received; ack has been returned read data byte or read data byte x x 0 0 0 0 0 1 data byte will be received; not ack bit will be returned data byte will be received; ack bit will be returned 88h previously addressed with own sla; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to not addressed slv mode; no recog- nition of own sla or general call address switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 switched to not addressed slv mode; no recog- nition of own sla or general call address. a start condition will be transmitted when the bus becomes free switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus be- comes free. 90h previously addressed with general call; data has been received; ack has been returned read data byte or read data byte x x 0 0 0 0 0 1 data byte will be received; not ack bit will be returned data byte will be received; ack bit will be returned 98h previously addressed with general call; data has been received; not ack has been returned read data byte or read data byte or 0 0 0 0 0 0 0 1 switched to not addressed slv mode; no recog- nition of own sla or general call address switched to not addressed slv mode; own sla will be recognized; general call address will be r ecog niz ed if s 1adr. 0 = l og i c 1
handshake solutions HT80C51 user manual peripheral modules ? i2c interface (sio1) page 68 of 132 ? philips electronics n.v. 2005 read data byte or read data byte 1 1 0 0 0 0 0 1 switched to not addressed slv mode; no recog- nition of own sla or general call address. a start condition will be transmitted when the bus becomes free switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus be- comes free. a0h a stop condition or repeated start condition has been received while still addressed as slv/rec or slv/trx no s1dat action or no s1dat action or no s1dat action or no s1dat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to not addressed slv mode; no recog- nition of own sla or general call address switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 switched to not addressed slv mode; no recog- nition of own sla or general call address. a start condition will be transmitted when the bus becomes free switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus be- comes free. [table 12] slave receiver mode
HT80C51 user manual peripheral modules ? i2c interface (sio1) handshake solutions ? philips electronics n.v. 2005 page 69 of 132 application software response to s1con status code s1sta status of the i2c bus and sio1 hardware to/from s1dat sta sto si aa next action taken by sio1 hardware a8h own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 0 0 0 1 last data byte will be transmitted; ack bit will be received data byte will transmitted; ack bit will be received b0h arbitration lost in sla+r/w as master; own sla+r has has been received; ack has been returned load data byte or load data byte x x 0 0 0 0 0 1 last data byte will be transmitted; ack bit will be received data byte will transmitted; ack bit will be received b8h data byte in s1dat has been transmitted; ack has been returned load data byte or load data byte x x 0 0 0 0 0 1 last data byte will be transmitted; ack bit will be received data byte will transmitted; ack bit will be received c0h data byte in s1dat has been transmitted; not ack has been returned no s1dat action or no s1dat action or no s1dat action or no s1dat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to not addressed slv mode; no recog- nition of own sla or general call address switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 switched to not addressed slv mode; no recog- nition of own sla or general call address. a start condition will be transmitted when the bus becomes free switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus be- comes free. c8h last data byte in s1dat has been transmitted (aa = 0); ack has been returned no s1dat action or no s1dat action or no s1dat action or no s1dat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to not addressed slv mode; no recog- nition of own sla or general call address switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 switched to not addressed slv mode; no recog- nition of own sla or general call address. a start condition will be transmitted when the bus becomes free switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus be- comes free. [table 13] slave transmitter mode
handshake solutions HT80C51 user manual peripheral modules ? i2c interface (sio1) page 70 of 132 ? philips electronics n.v. 2005 application software response to s1con status code s1sta status of the i2c bus and sio1 hardware to/from s1dat sta sto si aa next action taken by sio1 hardware f8h no relevant state informa- tion available; si = 0 no s1dat action no s1con action wait or proceed current transfer 00h bus error during mst or selected slave modes, due to an illegal start or stop condition. state 00h can also occur when interference causes sio1 to enter an undefined state. no s1dat action 0 1 0 x only the internal hardware is affected in the mst or addressed slv modes. in all cases, the bus is released and sio1 is switched to the not ad- dressed slv mode. sto is reset. [table 14] miscellaneous states 5.5.4.5. miscellaneous states there are two s1sta codes that do not correspond to a defi ned sio1 hardware state (see [table 14]). these are discussed below. s1sta = f8h this status code indicates that no relevant informat ion is available because the serial interrupt flag, si , is not yet set. this occurs between other states and when sio1 is not involved in a serial transfer. s1sta = 00h this status code indicates that a bus error has occu rred during an sio1 serial transfer. a bus error is caused when a start or stop condition occurs at an illegal position in the format frame. examples of such illegal positions ar e during the serial transf er of an address byte, a data byte, or an acknowl- edge bit. a bus error may also be caused when external interference disturbs the internal sio1 sig- nals. when a bus error occurs, si is set. to recover from a bus error, the sto flag must be set and si must be cleared. this causes sio1 to enter the ? not addressed? slave mode (a defined state) and to clear the sto flag (no other bits in s1con are affected). the sda and scl lines are released (a stop condition is nottransmitted). 5.5.4.6. some special cases the sio1 hardware ha s facilities to handle the following special cases that may occur during a serial transfer. simultaneous repeated start conditions from two masters a repeated start condition may be generated in the master transmitter or master receiver modes. a special case occurs if another master simult aneously generates a repeated start condition (see [figure 25]). until this occurs, arbitration is not lost by either master since they were both transmitting the same data. if the sio1 hardware detects a repeated start condition on the i2c bus before generating a re- peated start condition itself, it will release the bu s, and no interrupt request is generated. if another master frees the bus by generating a stop condit ion, sio1 will transmit a normal start condition (state 08h ), and a retry of the total serial data transfer can commence.
HT80C51 user manual peripheral modules ? i2c interface (sio1) handshake solutions ? philips electronics n.v. 2005 page 71 of 132 data transfer after loss of arbitration arbitration may be lost in the master transmitter and master receiver modes (see [figure 17]). loss of arbitration is indicated by the following states in s1sta : 38h , 68h , 78h , and b0h (see [figure 21] and [figure 22]). if the sta flag in s1con is set by the routines which service thes e states, then, if the bus is free again, a start condition (state 08h ) is transmitted without intervention by the cpu, and a retry of the total serial transfer can commence. forced access to the i2c bus in some applications, it may be possible for an unco ntrolled source to cause a bus hang-up. in such situations, the problem may be caused by interferen ce, temporary interruption of the bus or a tempo- rary short-circuit between sda and scl. if an uncontrolled source generates a superfluous start or masks a stop condition, then the i2c bus stays busy indef initely. if the sta flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the i2c bus is possible. this is achieved by setting the sto flag while the sta flag is still set. no stop condition is transmitted. the sio1 hardware behaves as if a stop condition was received and is able to transmit a start condition. the st0 flag is cleared by hardware (see [figure 26]). s sla w a data 18h reception of the own slave address and one or more data bytes all are acknowledged both masters continue with sla transmission a s 08h 28 h other master sends repeated start condition earlier [figure 25] simultaneous repeated start conditions from 2 masters
handshake solutions HT80C51 user manual peripheral modules ? i2c interface (sio1) page 72 of 132 ? philips electronics n.v. 2005 time out sta flag sda line scl line start condition [figure 26] forced access to a busy i2c bus i2c bus obstructed by a low level on scl or sda an i2c bus hang-up occurs if sda or scl is pulled low by an uncontrolled source. if the scl line is obstructed (pulled low) by a device on the bus, no further serial transfer is possible, and the sio1 hardware cannot resolve this type of problem. when this occurs, the problem must be resolved by the device that is pulling the scl bus line low. if the sda line is obstructed by another device on th e bus (e.g., a slave device out of bit synchroniza- tion), the problem can be solved by transmitting addi tional clock pulses on the scl line (see [figure 27]). the sio1 hardware transmits additional clock pulses when the sta flag is set, but no start condition can be generated because the sda line is pulled low while the i2c bus is considered free. the sio1 hardware attempts to generate a start condition after every two additional clock pulses on the scl line. when the sda line is eventually rel eased, a normal start condition is transmitted, state 08h is entered, and the serial transfer continues. if a forced bus access occurs or a repeated star t condition is transmitted while sda is obstructed (pulled low), the sio1 hardware performs the same action as described above. in each case, state 08h is entered after a successful start condition is tr ansmitted and normal serial transfer continues. note that the cpu is not involved in solving these bus hang-up problems. bus error a bus error occurs when a start or stop conditio n is present at an illegal position in the format frame. examples of illegal positions are during the se rial transfer of an address byte, a data, or an acknowledge bit. the sio1 hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. when a bus error is detected, sio1 immediately switches to the ?not ad- dressed? slave mode, releases the sda and scl lines , sets the interrupt flag, and loads the status register with 00h . this status code may be used to vector to a service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in [table 14].
HT80C51 user manual peripheral modules ? i2c interface (sio1) handshake solutions ? philips electronics n.v. 2005 page 73 of 132 sta flag sda line scl line (3) (1) (1) (2) start condition (1) unsuccessful attempt to send a start condition (2) sda line released (3) successful attempt to send a start condition; state 08h is entered. [figure 27] recovering from a bus obstruction caused by a low level on sda 5.5.5. slave-only version the description above covers the full featured vers ion of the ht-i2c module with master and slave modes. the slave-only version of the ht-i2c implements a subset of these features. this means, the slave-only version covers the behaviour and features as described for the complete version, but some features and pins are not implemented. it comprises ? no master transmit mode ? no master receiver mode ? no baud rate generator ? bits cr1 , cr2 , cr3 and sta in the sfr s1con are reserved ( 0 ) ? no clock input pin i2c_clk_i 5.5.6. application notes an i2c byte-oriented system driver is describ ed in application note an435. please visit http://www.semiconductors.philips.com/products/all_appnotes.html
handshake solutions HT80C51 user manual peripheral modules ? serial peripheral interface (spi) page 74 of 132 ? philips electronics n.v. 2005 5.6. serial peripheral interface (spi) this serial peripheral interface is a full-duplex , high-speed, synchronous communication bus with two operation modes: master mode and slav e mode. the main features are: ? full duplex, three-wire synchronous transfers ? master or slave operation ? four programmable master bit rates ? programmable clock polarity and phase ? end-of-transmission interrupt flag ? write collision flag protection 5.6.1. options the spi interface can be selected (ordered) by using option HT80C51_spi . 5.6.2. special function registers (spcr spsr spdr) spcr spi control register addr = f5h reset value = 0000 0100 bits 7 6 5 4 3 2 1 0 spie spe dwom mstr cpol cpha spr1 spr0 bit symbol function spcr.7 spie 1: 0: spi interrupt enable spi interrupt enabled: sfr bit spif causes an spi interrupt ( int_req_i[6] ) spi interrupt disabled: no spi interrupt generated spcr.6 spe 1: 0: spi interface enable spi interface enabled, output pin spi_spe_o is 1 spi interface disabled, output pin spi_spe_o is 0 spcr.5 dwom 1: 0: port d wire-or mode; connected to output pin spi_dwom_o . the environment can use the signal of this output pin to select the output mode: spi_dwom_o = 1 : use open drain outputs spi_dwom_o = 0 : use standard cmos outputs dwom is not used by the spi interface internally. spcr.4 mstr 1: 0: master mode select master mode slave mode spcr.3 cpol 1: 0: clock polarity; selects the polarity of the shift clock ( spi_sck_o in master mode, spi_sck_i in slave mode) (see [figure 29]) shift clock is active low shift clock is active high spcr.2 cpha 1: 0: clock phase as soon as input pin spi_ss_n_i goes low, the transaction begins and the first edge of spi_sck_i invokes the first data sample. if input pin spi_ss_n_i is 0 , the outputs are enabled. spcr.1 spcr.0 spr1 spr0 baudrate select bits. in master mode these bits select the clock divisor for generating the clock output spi_sck_o (see table below). in slave mode these bits have no effect.
HT80C51 user manual peripheral modules ? serial peripheral interface (spi) handshake solutions ? philips electronics n.v. 2005 page 75 of 132 spr1 spr0 baud rate 0 0 f spi_clk_i / 1 0 1 f spi_clk_i / 2 1 0 f spi_clk_i / 8 1 1 f spi_clk_i / 16 spsr spi status register addr = f6h reset value = 00h bits 7 6 5 4 3 2 1 0 spif wcol 0 0 0 0 0 0 bit symbol function spsr.7 spif 1: 0: spi data complete flag spif is set upon completion of a data transfer. if spif = 1 and sfr bit spie ( spcr.7 ) is set, an spi interrupt is generated. while spif is 1 , any write attempts to spdr are inhibitted until spdr is read. spif has to be cleared by software by reading spsr first and accessing spdr afterwards. spsr.6 wcol 1: 0: write collision flag set by hardware, when spdr is written while a data transfer is in pro- gress cleared by hardware, when first spsr is read and then spdr is ac- cessed. spsr.5 spsr.4 spsr.3 spsr.2 spsr.1 spsr.0 reserved bits write always 0 , read 0 spdr spi data register addr = f7h reset value = 00h bits 7 6 5 4 3 2 1 0 spdr bit symbol function spdr.7 .. spdr.0 data to transmit or received by the spi interface. the data register spdr is used to communicate transmit and receive data between the controller and the spi. transmit data is provided by writing to this register and receive data can be read from this register. only a wr ite to this register will initiate transmis- sion/reception of another byte, and this will onl y occur in the master device. at the com- pletion of transmitting a byte of data, the spif status bit is set in both the master and the slave devices. when the controller reads spdr , a buffer is actually read. the corresponding spif must be cleared by the time a second transfer of dat a from the shift register to the read buffer is initiated or an overrun condition will exist. in cases of overrun, the byte that causes the overrun is lost.
handshake solutions HT80C51 user manual peripheral modules ? serial peripheral interface (spi) page 76 of 132 ? philips electronics n.v. 2005 a write to spdr is not buffered; the data is directly stored into the shift register for trans- mission. 5.6.3. interrupts when a data transfer is completed, bit spif ( spsr.7 ) is set. if spif = 1 and sfr bit spie ( spcr.7 ) is set, an spi interrupt on interrupt line int6 is generated. spif has to be cleared by software by reading spsr first and accessing spdr afterwards. 5.6.4. operation [figure 28] shows a block diagram of the serial pe ripheral interface circuitry. when a master device transmits data to a slave device via the mosi line, the slave device responds by sending data to the master device via the master?s miso line. this im plies full duplex transmission with both data out and data in synchronized with the same clock signal. thus , the byte transmitted is replaced by the byte received and eliminates the need for separate trans mit-empty and receiver-full status bits. a single status bit ( spif ) is used to signify that the l/o operation has been completed. the spi is double buffered on read, but not on write. if a write is performed during data transfer, the transfer occurs uninterrupted, and the write will be unsuccessful. this condition will cause the write collision ( wcol ) status bit in the spsr to be set. after a data byte is shifted, the spif flag of the spsr is set.
HT80C51 user manual peripheral modules ? serial peripheral interface (spi) handshake solutions ? philips electronics n.v. 2005 page 77 of 132 divider by 1, 2, 8, 16 select spi control spi status register 8-bit shift register read data buffer clock logic spi control register spif wcol spi interrupt request mstr spe spie spi_mstr_o spi_spe_o spe dwon mstr cp ol cpha spr1 spr0 spr1 spr0 internal data bus spi clock (master) spi_clk_i spi_ss_n_i clock spi_sck_o spi_sck_i spi_mosi_i spi_mosi_o spi_miso_i spi_miso_o miso mosi sck ss [figure 28] spi block diagram in the master mode, the sck clock is driven to the output pin spi_sck_o . it idles high or low, depending on the cpol bit in the spcr , until data is written to the shift register, at which point eight clocks are generated to shift the eight bits of dat a and then sck goes idle again. data is shifted out thru output pin spi_mosi_o and shifted in from input pin spi_miso_i . in a slave mode, the slave start l ogic receives a logic low at pin spi_ss_n_i and the clock at input pin spi_sck_i . thus, the slave is synchronized with the ma ster. data from the master is received serially at the slave mosi line ( spi_mosi_i ) and loads the 8-bit shift r egister. after the 8-bit shift register is loaded, its data is para llel transferred to the read buffer. du ring a write cycle, data is written into the shift register, then the slave waits for a clo ck train from the master to shift the data out on the slave?s miso line ( spi_miso_o ). 5.6.4.1. bitlevel protocol master in slave out (miso) the miso line is configured as an input in a master device ( spi_miso_i ) and as an output in a slave device ( spi_miso_o ). it is used to transfer data from the slav e to the master, with the most significant bit sent first. the miso line of a slave device shoul d be placed in the high-impedance state if the slave is not selected.
handshake solutions HT80C51 user manual peripheral modules ? serial peripheral interface (spi) page 78 of 132 ? philips electronics n.v. 2005 master out slave in (mosi) the mosi line is configured as an output in a master device ( spi_mosi_o ) and as an input in a slave device ( spi_mosi_i ). it is used to transfer data from the ma ster to a slave, with the most significant bit sent first. serial clock (sck) the serial clock is used to synchronize data moveme nt both in and out of the device through its mosi and miso lines. the master and slave devices are c apable of exchanging a byte of information during a sequence of eight clock cycles. since the master device generates sck, this line becomes an input on a slave device ( spi_sck_i ) and an output at the master device ( spi_sck_o ). as shown in [figure 29], four possible timing relationships may be chosen by using control bits cpol and cpha in the serial peripheral control register ( spcr ). both master and slave devices must operate with the same timing. the master device always pl aces data on the mosi line a half-cycle before the clock edge (sck), in order for t he slave device to latch the data. two bits ( spr0 and spr1 ) in the spcr of the master device select t he clock rate. in a slave device, spr0 and spr1 have no effect on the operation of the spi. slave select (ss) the slave select input line ( spi_ss_n_i ) is used to select a slave device. it has to be low prior to data transactions and must stay low for the duration of the transaction. the spi_ss_n_i line on the master must be tied high. 1 2 3 4 5 6 7 8 msb 6 5 4 3 2 1 lsb 1 2 3 4 5 6 msb lsb sck cycle # (for reference) sck (cpol = 0) sck (cpol = 1) sample input (cpha = 0) data out sample input (cpha = 1) data out ss (to slave) [figure 29] data clock timing diagram when cpha = 0 , the shift clock is the or of spi_ss_n_i with sck. in this clock phase mode, spi_ss_n_i must go high between successive characters in an spi message. when cpha = 1 , spi_ss_n_i may be left low for several spi characters. in cases where there is only one spi slave, its spi_ss_n_i line could be tied to 0 as long as cpha = 1 clock modes are used. 5.6.4.2. standard interconnections due to data direction register control of spi outputs and the port d wire-or mode ( dwom ) option, the spi system can be configured in a variety of ways. sy stems with a single bidirectional data path rather than separate miso and mosi paths can be accommodated.
HT80C51 user manual peripheral modules ? serial peripheral interface (spi) handshake solutions ? philips electronics n.v. 2005 page 79 of 132 if the spi slaves can selectively disable their miso output, a broadcast message protocol is also pos- sible. 8-bit shift register spi clock generator 8-bit shift register master slave miso mosi spiclk port ss spiclk mosi miso [figure 30] spi single master single slave configuration
handshake solutions HT80C51 user manual peripheral modules ? watchdog timer (under development) page 80 of 132 ? philips electronics n.v. 2005 5.7. watchdog timer (under development) this module comprises an 8bit wa tchdog timer with prescaler. 5.7.1. options the watchdog timer can be selected (ordered) by using option t.b.d. . 5.7.2. special function registers (t3) t3 watchdog timer register addr = reset value = bits 7 6 5 4 3 2 1 0 t3 bit symbol function t3.7 .. t3.0 watchdog timer count register. specif ies the interval until the next timer overflow. writeable, when input wdt_ena_i = 1 . 5.7.3. interrupts no interrupts are generated. if the watchdog timer expires, a pulse on the reset output wdt_rst_o is generated. 5.7.4. operation the watchdog timer consists of an 11-bit prescaler and an 8-bit timer. it is controlled by the watchdog enable pin ( wdt_ena_i ). when wdt_ena_i = 1 , the timer is enabled and the power-down mode is disabled. when wdt_ena_i = 0 , the timer is disabled and the power- down mode is enabled. in the idle mode the watc hdog timer and reset circuitry remain active. the watchdog timer is shown in 0. the timer interval is derived from the frequency of clock input wdt_clk_i using the following formula: watchdog time interval = () i clk wdt f t _ _ 3 256 2048 ? when a timer overflow occurs, a rese t output pulse is generated at the pin wdt_rst_o for 3 clock cycles. to prevent a system reset the timer must be reloaded in time by the application software. if the proc- essor suffers a hardware/software malfunction, the softw are will fail to reload the timer. this failure will produce a reset upon overflow thus preventi ng the processor running out of control. the watchdog timer can only be reloaded if the condition flag wle ( pcon.4 ) has been previously set by software. at the moment the counter is loade d the condition flag is automatically cleared. the time interval between the timer reloading and the occurrence of a reset is dependent upon the reloaded value. for example, this time period may range from 2 ms to 500 ms when using a clock frequency f wdt_clk_i = 1 mhz.
HT80C51 user manual peripheral modules ? watchdog timer (under development) handshake solutions ? philips electronics n.v. 2005 page 81 of 132 [figure 31] functional diagram of the t3 watchdog timer
handshake solutions HT80C51 user manual peripheral modules ? triple-des converter page 82 of 132 ? philips electronics n.v. 2005 5.8. triple-des converter des stands for `data encryption standard? and is a widely used standard for enciphering and deci- phering blocks of data. this coprocessor can autonomously do a complete single- or triple- des en- cryption or decryption. features: ? two 56bit key registers ? 64bit text register for encryption and decryption ? single des encryption ? single des decryption ? triple des encryption ? triple des decryption 5.8.1. options the triple-des converter can be selected (ordered) by using option HT80C51_des . 5.8.2. special function registers (dcon dkey dtxt) dcon des control register (write only) addr = c0h reset value = xx bits 7 6 5 4 3 2 1 0 - - - - - dcmd bit symbol function dcon.7 dcon.6 dcon.5 dcon.4 dcon.3 - reserved bits write always 0, read 0 dcon.2 dcon.1 dcon.0 command for triple des-converter. for a list of commands, see table below. the dcon register is write-only. the value, which is written into dcon , determines the command for the triple-des converter. this command is started immediately after dcon has been written. dcmd command description 0 store key in key0 1 store key in key1 2 swap key0 and key1 3 reverse the order of bytes in text register 4 single-des encryption 5 single-des decryption 6 triple-des encryption 7 triple-des decryption
HT80C51 user manual peripheral modules ? triple-des converter handshake solutions ? philips electronics n.v. 2005 page 83 of 132 dkey des key register (write only) addr = c1h reset value = xx bits 7 6 5 4 3 2 1 0 dkey bit symbol function dkey.7 dkey.6 dkey.5 dkey.4 dkey.3 dkey.2 dkey.1 7bit slice of the key register. used to shift in a 56bit key, which can be stored in either key register key0 or key1 . dkey.0 ignored dtxt des data register addr = c2h reset value = xx bits 7 6 5 4 3 2 1 0 dtxt bit symbol function dtxt.7 .. dtxt.0 8bit slice of a complete 64bit data block for encryption or decryption. a write access shifts in 8bits, a read access shifts out 8bits. 5.8.3. interrupts no interrupts generated. 5.8.4. operation write accesses to all three registers are supported. however only read accesses from dtxt are sup- ported (read accesses from the other registers have no effect). each supported access on the 8-bit slice of either the key or the text register is foll owed by a permutation of the corresponding register. writing the 64-bit text register takes 8 write accesses to dtxt . reading the text register takes 8 read accesses from dtxt after which the contents of the text register are back in the original state. writing the 56-bit key register takes also 8 write accesses to dkey . in these accesses the least significant bit of each byte is discarded. to support triple des, the converte r has two internal key registers: key0 and key1 . after a key has been shifted in, its value has to be stored in key0 or key1 before it can be used. a single-des conver- sion uses key0 and a triple-des conversion uses first key0 , then key1 and finally key0 again. after a command has been written into dcon , it will be executed. only the three least significant bits in register dcon have a meaning. the conversions take so little time that no additional synchronization mechanism (interrupt or ready bit in status information) is needed. instead the hand shaking mechanism is used to obtain the required synchronization between the micro-co ntroller and the des converter. as long as the unit is busy in a conversion it does not accept any accesses to one of its sfrs. therefore after having given a conver- sion command, the micro-controller can immediately star t reading the resulting text. if in the case of a triple-des conversion the result is not yet available, the first read access is held up in a handshake until the conversion is completed (no busy waiting).
handshake solutions HT80C51 user manual peripheral modules ? triple-des converter page 84 of 132 ? philips electronics n.v. 2005 5.8.5. software view for an encryption or decryption using the triple-d es module, the following steps are neccesary: ? store the key in the key register (or both keys for triple-des) ? write the text into the des module ? start the encryption or decryption ? read the encrypted or decrypted text these steps are described in further detail below. 5.8.5.1. storing a key into auxiliary register key the key b1b2b3b4b5b6b7b8 can be stored in key register key0 or key1 by writing the sequence b8 b7 b6 b5 b4 b3 b2 b1 to sfr dkey . then the contents of dkey can be copied into key0 , by writing 00h to dcon , or it can be copied to key1 by writing 01h to dcon . 5.8.5.2. writing a text into the triple-des module the text 3d9d3fa9fc8ad337 can be transferred to the des module by writing the sequence 37 d3 8a fc a9 3f 9d 3d to sfr dtxt . alternatively the reverse sequence 3d 9d 3f a9 fc 8a d3 37 can be written to dtxt followed by the command 03h to dcon , which reverses the order of the bytes. 5.8.5.3. des encryption or decryption all encryptions or decryptions, be it single-des or triple-des, can be simply performed by writing the apporopiate command into the sfr dcon . the single-des encryption or decryption uses key0 only. the triple-des encryption and decryption use first key0 , then key1 and finally key0 . 5.8.5.4. reading the text result from register the triple-des module if the generated text result is 3d9d3fa9fc8ad337 reading from dtxt will deliver the sequence 37 d3 8a fc a9 3f 9d 3d after which the internal register will again contain the original text result. the text can also be read in the reverse or der by first giving the reverse-text command.
HT80C51 user manual peripheral modules ? triple-des converter handshake solutions ? philips electronics n.v. 2005 page 85 of 132 5.8.5.5. examples a single des encryption with key b1b2b3b4b5b6b7b8 and plain text 3d9d3fa9fc8ad337 can be done using following code: ; store key in key0 mov dkey, #b8h mov dkey, #b7h mov dkey, #b6h mov dkey, #b5h mov dkey, #b4h mov dkey, #b3h mov dkey, #b2h mov dkey, #b1h mov dcon, #00h ; write plain text into dtxt mov dtxt, #37h mov dtxt, #d3h mov dtxt, #8ah mov dtxt, #fch mov dtxt, #a9h mov dtxt, #3fh mov dtxt, #9dh mov dtxt, #3dh ; invoke a single-des encrytion mov dcon, #4 ; the generated cipher text is f64e59b5b5a36506 ; reading the result: mov r0, dtxt mov r1, dtxt mov r2, dtxt mov r3, dtxt mov r4, dtxt mov r5, dtxt mov r6, dtxt mov r7, dtxt ; will result with value 06h in r0, 65h in r1, etc.
handshake solutions HT80C51 user manual peripheral modules ? triple-des converter page 86 of 132 ? philips electronics n.v. 2005 sometimes the text is in a diffe rent (reversed) byte order. then following sequence can be used: ; store key in key0 (the byte order of the keys cannot be changed) mov dkey, #b8h mov dkey, #b7h mov dkey, #b6h mov dkey, #b5h mov dkey, #b4h mov dkey, #b3h mov dkey, #b2h mov dkey, #b1h mov dcon, #00h ; write plain text into dtxt (reversed order) mov dtxt, #3dh mov dtxt, #9dh mov dtxt, #3fh mov dtxt, #a9h mov dtxt, #fch mov dtxt, #8ah mov dtxt, #d3h mov dtxt, #37h mov dcon, #3 ; reverse byte order ; invoke a single-des encrytion mov dcon, #4 ; the generated cipher text is f64e59b5b5a36506 ; reading the result (reversed order) mov dcon, #3 ; reverse byte order for read-out mov r7, dtxt mov r6, dtxt mov r5, dtxt mov r4, dtxt mov r3, dtxt mov r2, dtxt mov r1, dtxt mov r0, dtxt ; will result with value 06h in r0, 65h in r1, etc.
HT80C51 user manual 80c51 family instruction set ? 80c51 instruction set summary handshake solutions ? philips electronics n.v. 2005 page 87 of 132 6. 80c51 family instruction set 6.1. 80c51 instruction set summary instructions that affect flag settings (1) instruction flag instruction flag c ov ac c ov ac add x x x clr c 0 addc x x x cpl c x subb x x x anl c,bit x mul 0 x anl c,/bit x div 0 x orl c,bit x da x orl c,/bit x rrc x mov c,bit x rlc x cjne x setb c 1 (1) note that operations on sfr byte address 208 or bit addr esses 209-215 (i.e., the psw or bits in the psw) will also affect flag settings. notes on instruction set and addressing modes: rn register r7-r0 of the currently selected register bank. direct 8-bit internal data location?s address. this could be an internal data ram location (0-127) or a sfr [i.e., i/o port, control register, status register, etc. (128-255)]. @ri 8-bit internal data ram location (0-255) addre ssed indirectly through register r1 or r0. #data 8-bit constant included in the instruction. #data 16 16-bit constant included in the instruction addr 16 16-bit destination address. used by lcall and ljmp. a branch can be anywhere within the 64k-byte program memory address space. addr 11 11-bit destination address. used by acall and ajmp. the branch will be within the same 2k-byte page of program memory as the first byte of the following instruction. rel signed (two?s complement) 8-bit offset byte. us ed by sjmp and all conditional jumps. range is ?128 to +127 bytes relative to first byte of the following instruction. bit direct addressed bit in internal data ram or special function register.
handshake solutions HT80C51 user manual 80c51 family instruction set ? 80c51 instruction set summary page 88 of 132 ? philips electronics n.v. 2005 mnemonic description byte machine cycles arithmetic operations add a,rn add register to accumulator 1 1 add a,direct add direct byte to accumulator 2 1 add a,@ri add indirect ram to accumulator 1 1 add a,#data add immediate data to accumulator 2 1 addc a,rn add register to accumulator with carry 1 1 addc a,direct add direct byte to accumulator with carry 2 1 addc a,@ri add indirect ram to accumulator with carry 1 1 addc a,#data add immediate data to accumulator with carry 2 1 subb a,rn add register to accumulator with borrow 1 1 subb a,direct add direct byte to accumulator with borrow 2 1 subb a,@ri add indirect ram to accumulator with borrow 1 1 subb a,#data add immediate data to accumulator with borrow 2 1 inc a increment accumulator 1 1 inc rn rn increment register 1 1 inc direct increment direct byte 2 1 inc @ri increment indirect ram 1 1 dec a decrement accumulator 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 1 dec @ri decrement indirect ram 1 1 inc dptr increment data pointer 1 2 mul ab multiply a and b 1 4 div ab divide a by b 1 4 da a decimal adjust accumulator 1 1 logical operations anl a,rn and register to accumulator 1 1 anl a,direct and direct byte to accumulator 2 1 anl a,@ri and indirect ram to accumulator 1 1 anl a,#data and immediate data to accumulator 2 1 anl direct,a and accumulator to direct byte 2 1 anl direct,#data and immediate data to direct byte 3 2 orl a,rn or register to accumulator 1 1 orl a,direct or direct byte to accumulator 2 1 orl a,@ri or indirect ram to accumulator 1 1 orl a,#data or immediate data to accumulator 2 1 orl direct,a or accumulator to direct byte 2 1 orl direct,#data or immediate data to direct byte 3 2 xrl a,rn exclusive-or register to accumulator 1 1 xrl a,direct exclusive-or direct byte to accumulator 2 1
HT80C51 user manual 80c51 family instruction set ? 80c51 instruction set summary handshake solutions ? philips electronics n.v. 2005 page 89 of 132 mnemonic description byte machine cycles logical operations (continued) xrl a,@ri exclusive-or indirect ram to accumulator 1 1 xrl a,#data exclusive-or immediate data to accumulator 2 1 xrl direct,a exclusive-or accumulator to direct byte 2 1 xrl direct,#data exclusive-or imm ediate data to direct byte 3 2 clr a clear accumulator 1 1 cpl a complement accumulator 1 1 rl a rotate accumulator left 1 1 rlc a rotate accumulator left through the carry 1 1 rr a rotate accumulator right 1 1 rrc a rotate accumulator right through the carry 1 1 swap a swap nibbles within the accumulator 1 1 data transfer mov a,rn move register to accumulator 1 1 mov a,direct move direct byte to accumulator 2 1 mov a,@ri move indirect ram to accumulator 1 1 mov a,#data move immediate data to accumulator 2 1 mov rn,a move accumulator to register 1 1 mov rn,direct move direct byte to register 2 2 mov rn,#data move immediate data to register 2 1 mov direct,a move accumulator to direct byte 2 1 mov direct,rn move register to direct byte 2 2 mov direct,direct move direct byte to direct 3 2 mov direct,@ri move indirect ram to direct byte 2 2 mov direct,#data move immediate data to direct byte 3 2 mov @ri,a move accumulator to indirect ram 1 1 mov @ri,direct move direct byte to indirect ram 2 2 mov @ri,#data move immediate data to indirect ram 2 1 mov dptr,#data16 load data pointer with a 16-bit constant 3 2 movc a,@a+dptr move code byte relative to dptr to a cc 1 2 movc a,@a+pc move code byte relative to pc to a cc 1 2 movx a,@ri move external ram (8-bit addr) to a cc 1 2 movx a,@dptr move external ram (16-bit addr) to a cc 1 2 movx a,@ri,a move a cc to external ram (8-bit addr) 1 2 movx @dptr,a move a cc to external ram (16-bit addr) 1 2 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a,rn exchange register with accumulator 1 1 xch a,direct exchange direct byte with accumulator 2 1 xch a,@ri exchange indirect ram with accumulator 1 1 xchd a,@ri exchange low-order digit indirect ram with a cc 1 1
handshake solutions HT80C51 user manual 80c51 family instruction set ? 80c51 instruction set summary page 90 of 132 ? philips electronics n.v. 2005 mnemonic description byte machine cycles boolean variable manipulation clr c clear carry 1 1 clr bit clear direct bit 2 1 setb c set carry 1 1 setb bit set direct bit 2 1 cpl c complement carry 1 1 cpl bit complement direct bit 2 1 anl c,bit and direct bit to carry 2 2 anl c,/bit and complement of direct bit to carry 2 2 orl c,bit or direct bit to carry 2 2 orl c,/bit or complement of direct bit to carry 2 2 mov c,bit move direct bit to carry 2 1 mov bit,c move carry to direct bit 2 2 jc rel jump if carry is set 2 2 jnc rel jump if carry not set 2 2 jb rel jump if direct bit is set 3 2 jnb rel jump if direct bit is not set 3 2 jbc bit,rel jump if direct bit is set and clear bit 3 2 program branching acall addr11 absolute subroutine call 2 2 lcall addr16 long subroutine call 3 2 ret return from subroutine 1 2 reti return from interrupt 1 2 ajmp addr11 absolute jump 2 2 ljmp addr16 long jump 3 2 sjmp rel short jump (relative addr) 2 2 jmp @a+dptr jump indirect relative to the dptr 1 2 jz rel jump if accumulator is zero 2 2 jnz rel jump if accumulator is not zero 2 2 cjne a,direct,rel compare direct byte to a cc and jump if not equal 3 2 cjne a,#data,rel compare immediate to a cc and jump if not equal 3 2 cjne rn,#data,rel compare immediate to register and jump if not equal 3 2 cjne @ri,#data,rel compare immediate to indirect and jump if not equal 3 2 djnz rn,rel decrement register and jump if not zero 2 2 djnz direct,rel decrement direct byte and jump if not zero 3 2 nop no operation 1 1 all mnemonics copyrighted ? intel corporation 1980
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 91 of 132 6.2. instruction definitions acall addr11 function: absolute call description: acall unconditionally calls a subroutine located at the indicated address. the instruction incre- ments the pc twice to obtain the address of the fo llowing instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increm ents the stack pointer twice. the destination ad- dress is obtained by successively concatenating the five high-order bits of the incremented pc, opcode bits 7-5, and the second byte of the instru ction. the subroutine ca lled must therefore start within the same 2k block of the program memory as the first byte of t he instruction following acall. no flags are affected. example: initially sp equals 07h. the label ?subrtn? is at program memory location 0345 h. after execut- ing the instruction, acall subrtn at location 0123h, sp will contain 09h, internal ram locations 08h and 09h will contain 25h and 01h, respectively, and the pc will contain 0345h. bytes: 2 cycles: 2 encoding: operation: acall (pc) (pc) + 2 (sp) (sp) + 1 (sp) (pc 7-0 ) (sp) (sp) + 1 (sp) (pc 15-8 ) (pc 10-0 ) page address a10 a9 a8 1 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 92 of 132 ? philips electronics n.v. 2005 add a, function: add description: add adds the byte variable indicated to the accumulator, leaving the result in the accumulator. the carry and auxiliary-carry flags are set, respective ly, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. when adding unsigned integers, the carry flag indicates an overflow oc- curred. ov is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6; oth- erwise ov is cleared. when adding signed integers, ov indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands. four source operand addressing modes are allowed: register, direct, register-indirect, or immedi- ate. example: the accumulator holds 0c3h (11000011b) and regi ster 0 holds 0aah (10101010b). the instruc- tion, add a,r0 will leave 6dh (01101101b) in the accumulator with the ac flag cleared and both the carry flag and ov set to 1. add a,rn bytes: 1 cycles: 1 encoding: operation: add (a) (a) + (r n ) add a,direct bytes: 2 cycles: 1 encoding: operation: add (a) (a) + (direct) add a,@ri bytes: 1 cycles: 1 encoding: operation: add (a) (a) + ((r i )) add a,#data bytes: 2 cycles: 1 encoding: operation: add (a) (a) + #data 0 0 1 0 1 r r r 0 0 1 0 0 1 0 1 direct address 0 0 1 0 0 1 1 i 0 0 1 0 0 1 0 0 immediate data
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 93 of 132 addc a, function: add with carry description: addc simultaneously adds the byte variable indi cated, the carry flag and the accumulator con- tents, leaving the result in the accumulator. the carry and auxiliary-carry flags are set, respec- tively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. when adding unsigned inte- gers, the carry flag indicates an overflow occurred. ov is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of bit 6; otherwise ov is cleared. when adding signed integers, ov indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands. four source operand addressing modes are allowed: register, direct, register-indirect, or immedi- ate. example: the accumulator holds 0c3h (11000011b) and register 0 holds 0aah (10101010b) with the carry flag set. the instruction, addc a,r0 will leave 6eh (01101110b) in the accumulator with ac cleared and both the carry flag and ov set to 1. addc a,rn bytes: 1 cycles: 1 encoding: operation: addc (a) (a) + (c) + (r n ) addc a,direct bytes: 2 cycles: 1 encoding: operation: addc (a) (a) + (c) + (direct) addc a,@ri bytes: 1 cycles: 1 encoding: operation: addc (a) (a) + (c) + ((r i )) addc a,#data bytes: 2 cycles: 1 encoding: operation: addc (a) (a) + (c) + #data 0 0 1 1 1 r r r 0 0 1 1 0 1 0 1 direct address 0 0 1 1 0 1 1 i 0 0 1 1 0 1 0 0 immediate data
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 94 of 132 ? philips electronics n.v. 2005 ajmp addr11 function: absolute jump description: ajmp transfers program execution to the indicate d address, which is formed at run-time by con- catenating the high-order five bits of the pc ( after incrementing the pc twice), opcode bits 7-5, and the second byte of the instruction. the destina tion must therefore be within the same 2k block of program memory as the first byte of the instruction following ajmp. example: the label ?jmpadr? is at program memory location 0123h. the instruction, ajmp jmpadr is at location 0345h and will load the pc with 0123h. bytes: 2 cycles: 2 encoding: operation: ajmp (pc) (pc) + 2 (pc 10-0 ) page address anl , function: logical-and for byte variables description: anl performs the bitwise logical-and operation between the variables indicated and stores the results in the destination variable. no flags are affected. the two operands allow six addressing mode comb inations. when the desti nation is the accumu- lator, the source can use register, direct, regist er-indirect, or immediate addressing; when the des- tination is a direct address, the source ca n be the accumulator or immediate data. note: when this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. example: if the accumulator holds 0c3h (11000011b) and re gister 0 holds 55h (01010101b) then the in- struction, anl a,r0 will leave 41h (01000001b) in the accumulator. when the destination is a directly addressed byte, this instruction will clear combinations of bits in any ram location or hardware register. the mask byte determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in the accu- mulator at run-time. the instruction, anl p1,#01110011b will clear bits 7, 3, and 2 of output port 1. a10 a9 a8 0 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 95 of 132 anl a,rn bytes: 1 cycles: 1 encoding: operation: anl (a) (a) (r n ) anl a ,direct bytes: 2 cycles: 1 encoding: operation: anl (a) (a) (direct) anl a,@ri bytes: 1 cycles: 1 encoding: operation: anl (a) (a) ((r i )) anl a,#data bytes: 2 cycles: 1 encoding: operation: anl (a) (a) #data anl direct,a bytes: 2 cycles: 1 encoding: operation: anl (a) ( direct) (a) anl direct,#data bytes: 3 cycles: 2 encoding: operation: anl (direct) ( direct) #data 0 1 0 1 1 r r r 0 1 0 1 0 1 0 1 direct address 0 1 0 1 0 1 1 i 0 1 0 1 0 1 0 0 immediate data 0 1 0 1 0 0 1 0 direct address 0 1 0 1 0 0 1 1 direct address immediate data
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 96 of 132 ? philips electronics n.v. 2005 anl c, function: logical-and for bit variables description: if the boolean value of the source bit is a logica l 0 then clear the carry flag; otherwise leave the carry flag in its current state. a slash (?/?) preceding the operand in the assembly language indi- cates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. no other flags are affected. only direct addressing is allowed for the source operand. example: set the carry flag if, and only if, p1.0 = 1, acc.7 = 1, and ov = 0: mov c,p1.0 ;load carry with input pin state anl c,acc.7 ;and carry with accum. bit 7 anl c,/ov ;and with inverse of overflow flag anl c,bit bytes: 2 cycles: 2 encoding: operation: anl (c) (c) (bit) anl c,/bit bytes: 2 cycles: 2 encoding: operation: anl (c) (c) ? (bit) 1 0 0 0 0 0 1 0 bit address 1 0 1 1 0 0 0 0 bit address
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 97 of 132 cjne ,,rel function: compare and jump if not equal description: cjne compares the magnitudes of the first two operands, and branches if their values are not equal. the branch destination is computed by add ing the signed relative-displacement in the last instruction byte to the pc, after incrementing the pc to the start of the next instruction. the carry flag is set if the unsigned integer value of is less than the unsigned integer value of ; otherwise, the carry is cl eared. neither operand is affected. the first two operands allow four addressing mode combinations: the accumulator may be com- pared with any directly addressed byte or immedi ate data, and any indirect ram location or work- ing register can be compared with an immediate constant. example: the accumulator contains 34h. register 7 contai ns 56h. the first instru ction in the sequence, cjne r7,#60h,not_eq ; ... .... ; r7 = 60h. not_eq: jc req_low ; if r7 < 60h. ; ... .... ; r7 > 60h. sets the carry flag and branches to the instruction at label not_eq. by testing the carry flag, this instruction determines whether r7 is greater or less than 60h. if the data being presented to port 1 is also 34h, then the instruction, wait: cjne a,p1,wait clears the carry flag and continues with the next instruction in sequence, since the accumulator does equal the data read from p1. (if some other value was being input on p1, the program will loop at this point until the p1 data changes to 34h.) cjne a,direct,rel bytes: 3 cycles: 2 encoding: operation: (pc) (pc) + 3 if (a) < > (direct) then (pc) (pc) + relative offset if (a) < (direct) then (c) 1 else (c) 0 1 0 1 1 0 1 0 1 direct address rel. address
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 98 of 132 ? philips electronics n.v. 2005 cjne a,#data,rel bytes: 3 cycles: 2 encoding: operation: (pc) (pc) + 3 if (a) < > data then (pc) (pc) + relative offset if (a) < data then (c) 1 else (c) 0 cjne rn,#data,rel bytes: 3 cycles: 2 encoding: operation: (pc) (pc) + 3 if (r n ) < > data then (pc) (pc) + relative offset if (r n ) < data then (c) 1 else (c) 0 cjne @ri,#data,rel bytes: 3 cycles: 2 encoding: operation: (pc) (pc) + 3 if ((r i )) < > data then (pc) (pc) + relative offset if ((r i )) < data then (c) 1 else (c) 0 1 0 1 1 0 1 0 0 immediate data rel. address 1 0 1 1 1 r r r immediate data rel. address 1 0 1 1 0 1 1 i immediate data rel. address
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 99 of 132 clr a function: clear accumulator description: the accumulator is cleared (all bits rese t to zero). no flags are affected. example: the accumulator contains 5ch (01011100b). the instruction, clr a will leave the accumulator set to 00h (00000000b). bytes: 1 cycles: 1 encoding: operation: clr (a) 0 clr bit function: clear bit description: the indicated bit is cleared (reset to zero). no other flags are affected. clr can operate on the carry flag or any directly addressable bit. example: port 1 has previously been written wi th 5dh (01011101b). the instruction, clr p1.2 will leave the port set to 59h (01011001b). clr c bytes: 1 cycles: 1 encoding: operation: clr (c) 0 clr bit bytes: 2 cycles: 1 encoding: operation: clr (bit) 0 1 1 1 0 0 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 bit address
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 100 of 132 ? philips electronics n.v. 2005 cpl a function: complement accumulator description: each bit of the accumulator is logically complemented (one?s complement). bits which previously contained a one are changed to a zero and vice-versa. no flags are affected. example: the accumulator contains 5ch (01011100b). the instruction, cpl a will leave the accumulator set to 0a3h (10100011b). bytes: 1 cycles: 1 encoding: operation: cpl (a) ? (a) cpl bit function: complement bit description: the bit variable specified is complemented. a bit which had been a one is changed to zero and vice-versa. no other flags are affected. cpl can operate on the carry or any directly addressable bit. note: when this instruction is used to modify an out put pin, the value used as the original data will be read from the output data latch, not the input pin. example: port 1 has previously been written with 5dh (01011101b). the instruction sequence, cpl p1.1 cpl p1.2 will leave the port set to 5bh (01011011b). cpl c bytes: 1 cycles: 1 encoding: operation: cpl (c) ? (c) cpl bit bytes: 2 cycles: 1 encoding: operation: cpl (bit) ? (bit) 1 1 1 1 0 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1 0 0 1 0 bit address
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 101 of 132 da a function: decimal-adjust accumulator for addition description: da a adjusts the eight-bit value in the accumulator resulting from the earlier addition of two vari- able (each in packed-bcd format), producing two f our-bit digits. any add or addc instruction may have been used to perform the addition. if accumulator bits 3-0 are greater than nine (xxx 1010-xxx1111), or if the ac flag is one, six is added to the accumulator, producing the proper bcd digit in the low-order nibble. this internal addition would set the carry flag if a carry-out of the low-order four-bit field propagated through all high-order bits, but it would not clear the carry flag otherwise. if the carry flag is now set, or if the four high-or der bits now exceed nine (1010xxx-111xxxx), these high-order bits are incremented by six, produci ng the proper bcd digit in the high-order nibble. again, this would set the carry flag if there was a carry-out of the high-order bits, but wouldn?t clear the carry. the carry flag thus indicates if t he sum of the original two bcd variables is greater than 100, allowing multiple precision dec imal addition. ov is not affected. all of this occurs during the one in struction cycle. essentially, this instruction performs the decimal conversion by adding 00h, 06h, 60h, or 66h to the accumulator, depending on initial accumula- tor and psw conditions. note: da a cannot simply convert a hexadecimal nu mber in the accumulator to bcd notation, nor does da a apply to decimal subtraction. example: the accumulator holds the value 56h (01010110b ) representing the packed bcd digits of the decimal number 56. register 3 contains the value 67h (01100111b) representing the packed bcd digits of the decimal num ber 67. the carry flag is se t.. the instruct ion sequence, addc a,r3 da a will first perform a standard two?s-complement binary addition, resulting in the value 0beh (10111110b) in the accumulator. the carry and auxiliary carry flags will be cleared. the decimal adjust instruction will then alter t he accumulator to the value 24h (00100100b), indi- cating the packed bcd digits of the decimal number 24, the low-order two digits of the decimal sum of 56, 67, and the carry-in. the carry flag wi ll be set by the decimal adjust instruction, indicating that a decimal overflow oc curred. the true sum 56, 67, and 1 is 124. bcd variables can be incremented or decremented by adding 01h or 99h. if the accumulator ini- tially holds 30h (representing the digits of 30 decimal), the the instruction sequence, add a,#99h da a will leave the carry set and 29h in the accumulator, since 30 + 99 = 129. the low-order byte of the sum can be interpreted to mean 30 ? 1 = 29. bytes: 1 cycles: 1 encoding: operation: da ?contents of accumulator are bcd if [[(a 3-0 ) > 9] [(ac) = 1]] then (a 3-0 ) (a 3-0 ) + 6 and if [[(a 7-4 ) > 9] [(c) = 1]] then (a 7-4 ) (a 7-4 ) + 6 1 1 0 1 0 1 0 0
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 102 of 132 ? philips electronics n.v. 2005 dec byte function: decrement description: the variable indicated is decremented by 1. an or iginal value of 00h will underflow to 0ffh. no flags are affected. four operand addressing modes are allowed: accu mulator, register, direct, or register-indirect. note: when this instruction is used to modify an output port, the value used as the original data will be read from the output da ta latch, not the input pin. example: register 0 contains 7fh (01111111b). inter nal ram locations 7eh and 7fh contain 00h and 40h, respectively. the instruction sequence, dec @r0 dec r0 dec @r0 will leave register 0 set to 7eh and internal ram locations 7eh and 7fh set to 0ffh and 3fh. dec a bytes: 1 cycles: 1 encoding: operation: dec (a) (a) ? 1 dec rn bytes: 1 cycles: 1 encoding: operation: dec (r n ) (r n ) ? 1 dec direct bytes: 2 cycles: 1 encoding: operation: dec (direct) (direct) ? 1 dec @ri bytes: 1 cycles: 1 encoding: operation: dec ((r i )) ((r i )) ? 1 0 0 0 1 0 1 0 0 0 0 0 1 1 r r r 0 0 0 1 0 1 0 1 direct address 0 0 0 1 0 1 1 i
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 103 of 132 div ab function: divide description: div ab divides the unsigned eight-bit integer in the accumulator by the unsigned eight-bit integer in register b. the accumulator receives the integer part of the qu otient; register b receives the integer remain- der. the carry and ov flags will be cleared. exception: if b had originally contained 00h, the values returned in the accumulator and b- register will be undefined and the overflow flag will be set. the carry flag is cleared in any case. example: the accumulator contains 251 (0fbh or 1111101 1b) and b contains 18 (12h or 00010010b). the instruction, div ab will leave 13 in the accumulator (0dh or 00001101b) and the value 17 (11h or 00010001b) in b, since 251 = (13 x 18) + 17. carry and ov will both be cleared. bytes: 1 cycles: 4 encoding: operation: div (a) 15-8 (a)/(b) (b) 7-0 1 0 0 0 0 1 0 0
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 104 of 132 ? philips electronics n.v. 2005 djnz , function: decrement and jump if not zero description: djnz decrements the location indicated by 1, and branches to the address indicated by the sec- ond operand if the resulting value is not zero. an or iginal value of 00h will underflow to 0ffh. no flags are affected. the branch destination woul d be computed by adding the signed relative- displacement value in the last instruction byte to the pc, after incrementing t he pc to the first byte of the following instruction. the location decr emented may be a register or directly addressed byte. note: when this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. example: internal ram locations 40h, 50h, and 60h contain the values 01h, 70h, and 15h, respectively. the instruction sequence, djnz 40h,label_1 djnz 50h,label_2 djnz 60h,label_3 will cause a jump to the instruction at label_2 wi th the values 00h, 6fh, and 15h in the three ram locations. the first jump was not taken because the result was zero. this instruction provides a simple was of execut ing a program loop a given number of times, or for adding a moderate time delay (from 2 to 512 machine cycles) ith a single instruction. the in- struction sequence, mov r2,#8 toggle: cpl p1.7 djnz r2,toggle will toggle p1.7 eight times, causing four output pulses to appear at bit 7 of output port 1. each pulse will last three machine cycles, two for djnz and one to alter the pin. djnz rn,rel bytes: 2 cycles: 2 encoding: operation: djnz (pc) (pc) + 2 (r n ) (r n ) ? 1 if (r n ) > 0 or (r n ) < 0 then (pc) (pc) + rel djnz direct,rel bytes: 3 cycles: 2 encoding: operation: djnz (pc) (pc) + 2 (direct) (direct) ? 1 if (direct) > 0 or (direct) < 0 then (pc) (pc) + rel 1 1 0 1 1 r r r rel. address 1 1 0 1 0 1 0 1 direct data rel. address
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 105 of 132 inc function: increment description: inc increments the indicated variable by 1. an or iginal value of 0ffh will overflow to 00h. no flags are affected. three addressing modes are al lowed: register, direct, or register-indirect. note: when this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. example: register 0 contains 7eh (01111110b). internal ram locations 7eh and 7fh contain 0ffh and 40h, respectively. the instruction sequence, inc @r0 inc r0 inc @r0 will leave register 0 set to 7fh and internal ram locations 7eh and 7fh holding (respectively) 00h and 41h. inc a bytes: 1 cycles: 1 encoding: operation: inc (a) (a) + 1 inc rn bytes: 1 cycles: 1 encoding: operation: inc (r n ) (r n ) + 1 inc direct bytes: 2 cycles: 1 encoding: operation: inc (direct) (direct) + 1 inc @ri bytes: 1 cycles: 1 encoding: operation: inc ((r i )) ((r i )) + 1 0 0 0 0 0 1 0 0 0 0 0 0 1 r r r 0 0 0 0 0 1 0 1 direct address 0 0 0 0 0 1 1 i
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 106 of 132 ? philips electronics n.v. 2005 inc dptr function: increment data pointer description: increment the 16-bit data pointer by 1. a 16-bit increment (modulo 2 16 ) is performed; an overflow of the low-order byte of the data pointer (dpl) from 0ffh to 00h will increment the high-order byte (dph). no flags are affected. this is the only 16-bit register which can be incremented. example: registers dph and dpl contain 12h and 0feh, respectively. the instruction sequence, inc dptr inc dptr inc dptr will change dph and dpl to 13h and 01h. bytes: 1 cycles: 2 encoding: operation: inc (dptr) (dptr) + 1 jb bit,rel function: jump if bit set description: if the indicated bit is a one, jump to the addre ss indicated; otherwise proceed with the next instruc- tion. the branch destination is computed by addi ng the signed relative-displacement in the third instruction byte to the pc, after in crementing the pc to the first byte of the next instruction. the bit tested is not modified. no flags are affected. example: the data present at input port 1 is 11001010b. the accumulator holds 56 (01010110b). the instruction sequence, jb p1.2,label1 jb acc.2,label2 will cause program execution to branch to the instruction at label label2. bytes: 3 cycles: 2 encoding: operation: jb (pc) (pc) + 3 if (bit) = 1 then (pc) (pc) + rel 1 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 bit address rel. address
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 107 of 132 jbc bit,rel function: jump if bit is set and clear bit description: if the indicated bit is a one, branch to the addres s indicated; otherwise proceed with the next in- struction. the bit will not be cleared if it is al ready a zero. the branch de stination is computed by adding the signed relative-displacement in the thir d instruction byte to the pc, after incrementing the pc to the first byte of the next instruction. no flags are affected. note: when this instruction is used to test an output pin, the value used as the original data will read from the output data la tch, not the input pin. example: the accumulator holds 56h (01010110b). the instruction sequence, jbc acc.3,label1 jbc acc.2,label2 will cause program execution to continue at the instruction identified by the label2, with the ac- cumulator modified to 52h (01010010b). bytes: 3 cycles: 2 encoding: operation: jbc (pc) (pc) + 3 if (bit) = 1 then (bit) 0 (pc) (pc) + rel jc rel function: jump if carry is set description: if the carry flag is set, branch to the address indicated; otherwise proceed with the next instruc- tion. the branch destination is computed by addi ng the signed relative-displacement in the sec- ond instruction byte to the pc, after incremen ting the pc twice. no flags are affected. example: the carry flag is cleared. the instruction sequence, jc label1 cpl c jc label2 will set the carry and cause program execution to c ontinue at the instruction identified by the label label2. bytes: 2 cycles: 2 encoding: operation: jc (pc) (pc) + 2 if (c) = 1 then (pc) (pc) + rel 0 0 0 1 0 0 0 0 bit address rel. address 0 1 0 0 0 0 0 0 rel. address
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 108 of 132 ? philips electronics n.v. 2005 jmp @a+dptr function: jump indirect description: add the eight-bit unsigned contents of the accumulator with the si xteen-bit data pointer, and load the resulting sum to the program counter. this will be the address for subsequent instruction fetches. sixteen-bit addition is performed (modulo 2 16 ): a carry-out from the low-order eight bits propa- gates through the higher-order bits. neither the a ccumulator nor the data pointer is altered. no flags are affected. example: an even number from 0 to 6 is in the accumulato r. the following sequence of instructions will branch to one of four ajmp instructions in a jump table starting at jmp_tbl: mov dptr,#jmp_tbl jmp @a+dptr jmp_tbl: ajmp label0 ajmp label1 ajmp label2 ajmp label3 if the accumulator equals 04h when starting this sequence, execut ion will jump to label label2. remember that ajmp is a two-byte instruction, so the jump instructions start at every other ad- dress. bytes: 1 cycles: 2 encoding: operation: jmp (pc) (a) + (dptr) jnb bit,rel function: jump if bit not set description: if the indicated bit is a zero, branch to the indi cated address; otherwise proceed with the next instruction. the branch destinatio n is computed by adding the signed relative-displacement in the third instruction byte to the pc, after incrementing t he pc to the first byte of the next instruction. the bit tested is not modified. no flags are affected. example: the data present at input port 1 is 11001010b . the accumulator holds 56h (01010110b). the instruction sequence, jnb p1.3,label1 jnb acc.3,label2 will cause program execution to continue at the instruction at label label2. bytes: 3 cycles: 2 encoding: operation: jnb (pc) (pc) + 3 if (bit) = 0 then (pc) (pc) + rel 0 1 1 1 0 0 1 1 0 0 1 1 0 0 0 0 bit address rel. address
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 109 of 132 jnc rel function: jump if carry not set description: if the carry flag is a zero, branch to the address i ndicated; otherwise procee d with the next instruc- tion. the branch destination is computed by addi ng the signed relative-displacement in the sec- ond instruction byte to the pc, after incrementing t he pc twice to point to the next instruction. the carry flag is not modified. example: the carry flag is set. the instruction sequence, jnc label1 cpl c jnc label2 will clear the carry and cause program execution to continue at the instructi on identified by the la- bel label2. bytes: 2 cycles: 2 encoding: operation: jnc (pc) (pc) + 2 if (c) = 0 then (pc) (pc) + rel jnz rel function: jump if accumu lator not zero description: if any bit of the accumulator is a one, branch to t he indicated address; otherwise proceed with the next instruction. the branch dest ination is computed by adding the signed relative-displacement in the second instruction byte to the pc, after incr ementing the pc twice. the accumulator is not modified. no flags are affected. example: the accumulator originally holds 00h. the instruction sequence, jnz label1 inc a jnz label2 will set the accumulator to 01h and continue at label label2. bytes: 2 cycles: 2 encoding: operation: jnz (pc) (pc) + 2 if a 0 then (pc) (pc) + rel 0 1 0 1 0 0 0 0 rel. address 0 1 1 1 0 0 0 0 rel. address
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 110 of 132 ? philips electronics n.v. 2005 jz rel function: jump if accumulator zero description: if all bits of the accumulator are zero, branch to the indicated address; otherwise proceed with the next instruction. the branch dest ination is computed by adding the signed relative-displacement in the second instruction byte to the pc, after incr ementing the pc twice. the accumulator is not modified. no flags are affected. example: the accumulator originally holds 01h. the instruction sequence, jz label1 dec a jz label2 will change the accumulator to 00h and cause pr ogram execution to cont inue at the instruction identified by th e label label2. bytes: 2 cycles: 2 encoding: operation: jz (pc) (pc) + 2 if a = 0 then (pc) (pc) + rel lcall addr16 function: long call description: lcall calls a subroutine located at the indicated address. the in struction adds three to the pro- gram counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing t he stack pointer by two. the high-order and low- order bytes of the pc are then loaded, respectively, with the second and third bytes of the lcall instruction. program execution c ontinues with the instruction at this address. the subroutine may therefore begin anywhere in the full 64k-byte program memory address space. no flags are af- fected. example: initially the stack pointer equals 07h. the label ?subrtn? is assigned to program memory loca- tion 1234h. after execut ing the instruction, lcall subrtn at location 0123h, the stack pointer will cont ain 09h, internal ram lo cations 08h and 09h will contain 26h and 01h, and the pc will contain 1235h. bytes: 3 cycles: 2 encoding: operation: lcall (pc) (pc) + 3 (sp) (sp) + 1 ((sp)) (pc 7-0 ) (sp) (sp) + 1 ((sp)) (pc 15-8 ) (pc) addr 15-0 0 1 1 0 0 0 0 0 rel. address 0 0 0 1 0 0 1 0 addr15-addr8 addr7-addr0
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 111 of 132 ljmp addr16 function: long jump description: ljmp causes an unconditional branch to the indi cated address, by loading the high-order and low-order bytes of the pc (respectively) with t he second and third instruction bytes. the destina- tion may therefore be anywhere in the full 64k progr am memory address space. no flags are af- fected. example: the label ?jmpadr? is assigned to the instructi on at program memory location 1234h. the in- struction, ljmp jmpadr at location 0123h will load the program counter with 1234h. bytes: 3 cycles: 2 encoding: operation: ljmp (pc) addr 15-0 mov , function: move byte variable description: the byte variable indicated by the second operand is copied into the location specified by the first operand. the source byte is not affected. no other register or flag is affected. this is by far the most flexible operation. fi fteen combinations of source and destination address- ing modes are allowed. example: internal ram location 30h holds 40h. the value of ram location 40h is 10h. the data present at input port 1 is 11001010b (0cah). the instruction sequence, mov r0,#30h ;r0 < = 30h mov a,@r0 ;a < = 40h mov r1,a ;r1 < = 40h mov b,@r1 ;b < = 10h mov @r1,p1 ;ram (40h) < = 0cah mov p2,p1 ;p2 #0cah leaves the value 30h in register 0, 40h in both t he accumulator and register 1, 10h in register b, and 0cah (11001010b) both in ram location 40h and output on port 2. mov a,rn bytes: 1 cycles: 1 encoding: operation: mov (a) (r n ) 0 0 0 0 0 0 1 0 addr15-addr8 addr7-addr0 1 1 1 0 1 r r r
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 112 of 132 ? philips electronics n.v. 2005 *mov a,direct bytes: 2 cycles: 1 encoding: operation: mov (a) (direct) mov a,@ri bytes: 1 cycles: 1 encoding: operation: mov (a) ((r i )) mov a ,#data bytes: 2 cycles: 1 encoding: operation: mov (a) #data mov rn,a bytes: 1 cycles: 1 encoding: operation: mov (r n ) (a) mov rn,direct bytes: 2 cycles: 2 encoding: operation: mov (r n ) (direct) mov rn,#data bytes: 2 cycles: 1 encoding: operation: mov (r n ) #data *mov a,acc is not a valid instruction. 1 1 1 0 0 1 0 1 direct address 1 1 1 0 0 1 1 i 0 1 1 1 0 1 0 0 immediate data 1 1 1 1 1 r r r 1 0 1 0 1 r r r direct address 0 1 1 1 1 r r r immediate data
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 113 of 132 mov direct,a bytes: 2 cycles: 1 encoding: operation: mov (direct) (a) mov direct,rn bytes: 2 cycles: 2 encoding: operation: mov (direct) (r n ) mov direct,direct bytes: 3 cycles: 2 encoding: operation: mov (direct) (direct) mov direct,@ri bytes: 2 cycles: 2 encoding: operation: mov (direct) ((r i )) mov direct,#data bytes: 3 cycles: 2 encoding: operation: mov (direct) #data mov @ri,a bytes: 1 cycles: 1 encoding: operation: mov ((r i )) (a) 1 0 0 0 1 r r r direct address 1 1 1 1 0 1 0 1 direct address 1 0 0 0 0 1 0 1 dir. addr. (src) dir. addr. (dest) 1 0 0 0 0 1 1 i direct address 0 1 1 1 0 1 0 1 direct address immediate data 1 1 1 1 0 1 1 i
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 114 of 132 ? philips electronics n.v. 2005 mov @ri,direct bytes: 2 cycles: 2 encoding: operation: mov ((r i )) (direct) mov @ri,#data bytes: 2 cycles: 1 encoding: operation: mov ((r i )) #data mov , function: move bit data description: the boolean variable indicated by the second operand is copied into the location specified by the first operand. one of the operands must be the ca rry flag; the other may be any directly address- able bit. no other register or flag is affected. example: the carry flag is originally set. the data present at input port 3 is 11000101b. the data previously written to output port 1 is 35h ( 00110101b). the instruction sequence, mov p1.3,c mov c,p3.3 mov p1.2,c will leave the carry cleared and change port 1 to 39h (00111001b). mov c,bit bytes: 2 cycles: 1 encoding: operation: mov (c) (bit) mov bit,c bytes: 2 cycles: 2 encoding: operation: mov (bit) (c) 1 0 1 0 0 1 1 i direct address 0 1 1 1 0 1 1 i immediate data 1 0 1 0 0 0 1 0 bit address 1 0 0 1 0 0 1 0 bit address
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 115 of 132 mov dptr,#data16 function: load data pointer with a 16-bit constant description: the data pointer is loaded with the 16-bit constant indicated. the 16-bit c onstant is loaded into the second and third bytes of the instruction. the second byte (dph) is the high-order byte, while the third byte (dpl) holds the low- order byte. no flags are affected. this is the only instruction whic h moves 16 bits of data at once. example: the instruction, mov dptr,#1234h will load the value 1234h into the data pointer: dph will hold 12h and dpl will hold 34h. bytes: 3 cycles: 2 encoding: operation: mov (dptr) (#data 15-0 ) dph dpl #data 15-8 #data 7-0 movc a,@a+ function: move code byte description: the movc instructions load the accumulator with a code byte, or constant from program mem- ory. the address of the byte fetched is the sum of the original unsigned eight-bit accumulator con- tents and the contents of a sixteen- bit base register, which may be either the data pointer or the pc. in the latter case, the pc is incremented to the address of the following instruction before be- ing added with the accumulator; otherwise the base register is not altered. sixteen-bit addition is performed so a carry-out from the low-order eight bits may propagate through higher-order bits. no flags are affected. example: a value between 0 and 3 is in the accumulator. the following instructions will translate the value in the accumulator to one of four values defined by the db (define byte) irective: rel_pc: inc a movc a,@a+pc ret db 66h db 77h db 88h db 99h if the subroutine is called with the accumulator equal to 01h, it will return with 77h in the accumu- lator. the inc a before the movc instruction is needed to ?get ar ound? the ret instruction above the table. if several bytes of code separated t he movc from the table, the corresponding number would be added to the accumulator instead. 1 0 0 1 0 0 0 0 imm. data 15-8 imm. data 7-0
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 116 of 132 ? philips electronics n.v. 2005 movc a,@a+dptr bytes: 1 cycles: 2 encoding: operation: movc (a) ((a) + (dptr)) movc a,@a+pc bytes: 1 cycles: 2 encoding: operation: movc (pc) (pc) + 1 (a) ((a) + (pc)) movx , function: move external description: the movx instructions transfer data between the accumulator and a byte of external data mem- ory, hence the ?x? appended to mov. there are two types of instructions, differing in whether they provide an eight-bit or sixteen-bit indirect address to the external data ram. in the first type, the contents of r0 or r1 in t he current register bank provide an eight-bit address. eight bits are sufficient for external i/o expansi on decoding or for a relatively small ram array. for somewhat larger arrays, the sfr xramp be used to define higher-order address bits. these pins would be set by a move instruction to xramp preceding the movx. in the second type of movx instruction, the data pointer generates a sixteen-bit address. this form is faster and more efficient when accessing very large data arrays (up to 64k bytes), since no additional instructions are ne eded to set up the output ports. it is possible in some situations to mix the two movx types. a large ram array with its high-order address lines can be addressed via the data pointe r, or with code to output high-order address bits to xramp followed by a movx instruction using r0 or r1. example: an external 256 byte ram using multiplexed addr ess/data lines is connected to the 8051. regis- ters 0 and 1 contain 12h and 34h. location 34h of the external ram holds the value 56h. the instruction sequence, movx a,@r1 movx @r0,a copies the value 56h into both the accumulator and external ram location 12h. movx a,@ri bytes: 1 cycles: 2 encoding: operation: movx (a) ((r i )) 1 0 0 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 1 i
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 117 of 132 movx a,@dptr bytes: 1 cycles: 2 encoding: operation: movx (a) ((dptr)) movx @ri,a bytes: 1 cycles: 2 encoding: operation: movx ((r i )) (a) movx @dptr,a bytes: 1 cycles: 2 encoding: operation: movx ((dptr)) (a) mul ab function: multiply description: mul ab multiplies the unsigned eight-bit integers in the accumulator and register b. the low- order byte of the sixteen-bit product is left in t he accumulator, and the high-order byte in b. if the product is greater than 255 (0ffh) the overflow flag is set; otherwise it is cleared. the carry flag is always cleared. example: originally the accumulator holds the value 80 (50h). register b holds the value 160 (0a0h).the instruction, mul ab will give the product 12,800 (3200h), so b is changed to 32h (00110010b) and the accumulator is cleared. the overflow flag is set, carry is cleared. bytes: 1 cycles: 4 encoding: operation: mul (a) 7-0 (a) x (b) (b) 15-8 1 1 1 0 0 0 0 0 1 1 1 1 0 0 1 i 1 1 1 1 0 0 0 0 1 0 1 0 0 1 0 0
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 118 of 132 ? philips electronics n.v. 2005 nop function: no operation description: execution continues at the following instruction. other than the pc, no registers or flags are af- fected. example: it is desired to produce a low-going output pulse on bit 7 of port 2 lasting exactly 5 cycles. a sim- ple setb/clr sequence would generate a one-cycle puls e, so four additional cycles must be in- serted. this may be done (assuming are en abled) with the instruction sequence, clr p2.7 nop nop nop nop setb p2.7 bytes: 1 cycles: 1 encoding: operation: nop (pc) (pc) + 1 orl , function: logical-or for byte variables description: orl performs the bitwise logical-or operation bet ween the indicated variables, storing the results in the destination byte. no flags are affected. the two operands allow six addressing mode comb inations. when the desti nation is the accumu- lator, the source can use register, direct, regist er-indirect, or immediate addressing; when the des- tination is a direct address, the source ca n be the accumulator or immediate data. note: when this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. example: if the accumulator holds 0c3h (11000011b) and r0 holds 55h (01010101b) then the instruction, orl a,r0 will leave the accumulator holding the value 0d7h (11010111b). when the destination is a di- rectly addressed byte, the instruction can set comb inations of bits in any ram location or hard- ware register. the pattern of bits to be set is determined by a mask byte, which may be either a constant data value in t he instruction or a variable computed in the accumulator at run-time. the instruction, orl p1,#00110010b will set bits 5, 4, and 1 of output port 1. orl a,rn bytes: 1 cycles: 1 encoding: operation: orl (a) (a) (r n ) 0 0 0 0 0 0 0 0 0 1 0 0 1 r r r
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 119 of 132 orl a,direct bytes: 2 cycles: 1 encoding: operation: orl (a) (a) (direct) orl a,@ri bytes: 1 cycles: 1 encoding: operation: orl (a) (a) ((r i )) orl a,#data bytes: 2 cycles: 1 encoding: operation: orl (a) (a) #data orl direct,a bytes: 2 cycles: 1 encoding: operation: orl (direct) (direct) (a) orl direct,#data bytes: 3 cycles: 2 encoding: operation: orl (direct) (direct) #data 0 1 0 0 0 1 0 1 direct address 0 1 0 0 0 1 1 i 0 1 0 0 0 1 0 0 immediate data 0 1 0 0 0 0 1 0 direct address 0 1 0 0 0 0 1 1 direct address immediate data
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 120 of 132 ? philips electronics n.v. 2005 orl c, function: logical-or for bit variables description: set the carry flag if the boolean value is a logical 1; leave the carry in it s current state otherwise. a slash (?/?) preceding the operand in the assembly language indicates that the logical comple- ment of the addressed bit is used as the source value, but the source bit itself is not affected. no other flags are affected. example: set the carry flag if and only if p1.0 = 1, acc.7 = 1, or ov = 0: orl c,p1.0 ;load carry with input pin p10 orl c,acc.7 ;or carry with the acc. bit 7 orl c,/ov ;or carry with the inverse of ov. orl c,bit bytes: 2 cycles: 2 encoding: operation: orl (c) (c) (bit) orl c,/bit bytes: 2 cycles: 2 encoding: operation: orl (c) (c) ? (bit) 0 1 1 1 0 0 1 0 bit address 1 0 1 0 0 0 0 0 bit address
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 121 of 132 pop direct function: pop from stack description: the contents of the internal ram location addresse d by the stack pointer is read, and the stack pointer is decremented by one. the value read is then transferred to the directly addressed byte indicated. no flags are affected. example: the stack pointer originally contains the value 32h, and internal ram locations 30h through 32h contain the values 20h, 23h, and 01h, re spectively. the instruction sequence, pop dph pop dpl will leave the stack pointer equal to the value 30h and the data pointer set to 0123h. at this point the instruction, pop sp will leave the stack pointer set to 20h. note that in this special case the stack pointer was dec- remented to 2fh before being load ed with the value popped (20h). bytes: 2 cycles: 2 encoding: operation: pop (direct) ((sp)) (sp) (sp) ? 1 push direct function: push onto stack description: the stack pointer is incremented by one. the cont ents of the indicated variable is then copied into the internal ram location addressed by the st ack pointer. otherwise no flags are affected. example: on entering an interrupt routine the stack pointer contains 09h. the data pointer holds the value 0123h. the instruction sequence, push dpl push dph will leave the stack pointer set to 0bh and store 23h and 01h in internal ram locations 0ah and 0bh, respectively. bytes: 2 cycles: 2 encoding: operation: push (sp) (sp) + 1 ((sp)) (direct) 1 1 0 1 0 0 0 0 direct address 1 1 0 0 0 0 0 0 direct address
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 122 of 132 ? philips electronics n.v. 2005 ret function: return from subroutine description: ret pops the high- and low-order bytes of the pc successively from the stack, decrementing the stack pointer by two. program execution continues at the resulting address, generally the instruc- tion immediately following an acall or lcall. no flags are affected. example: the stack pointer originally contains the value 0bh. internal ram locations 0ah and 0bh contain the values 23h and 01h, respectively. the instruction, ret will leave the stack pointer equal to the value 09h. program execution will continue at location 0123h. bytes: 1 cycles: 2 encoding: operation: ret (pc 15-8 ) ((sp)) (sp) (sp) ? 1 (pc 7-0 ) ((sp)) (sp) (sp) ? 1 reti function: return from interrupt description: reti pops the high- and low-order bytes of the pc successively from the stack, and restores the interrupt logic to accept additional interrupts at t he same priority level as the one just processed. the stack pointer is left decremented by two. no other registers are af fected; the psw is not automatically restored to its pre- interrupt status. program executio n continues at the resulting ad- dress, which is generally the instruction immediat ely after the point at which the interrupt request was detected. if a lower- or same-level interrupt has been pending when the reti instruction is executed, that one instruction will be executed before the pe nding interrupt is processed. example: the stack pointer originally contains the value 0bh. an interrupt was detected during the instruc- tion ending at location 0122h. internal ram lo cations 0ah and 0bh contain the values 23h and 01h, respectively. the instruction, reti will leave the stack pointer equal to 09h and return program execution to location 0123h. bytes: 1 cycles: 2 encoding: operation: reti (pc 15-8 ) ((sp)) (sp) (sp) ? 1 (pc 7-0 ) ((sp)) (sp) (sp) ? 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 123 of 132 rl a function: rotate accu mulator left description: the eight bits in the accumulator are rotated one bi t to the left. bit 7 is ro tated into the bit 0 posi- tion. no flags are affected. example: the accumulator holds the value 0c5h (11000101b). the instruction, rl a leaves the accumulator holding the value 8b h (10001011b) with the carry unaffected. bytes: 1 cycles: 1 encoding: operation: rl (a n+1 ) (a n ), n = 0 ? 6 (a0) (a7) rlc a function: rotate accumulator left through the carry flag description: the eight bits in the accumulato r and the carry flag ar e together rotate d one bit to the left. bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. no other flags are affected. example: the accumulator holds the value 0c5h (1100010 1b), and the carry is zero. the instruction, rlc a leaves the accumulator holding the value 8ah (10001010b) with the carry set. bytes: 1 cycles: 1 encoding: operation: rlc (a n+1 ) (a n ), n = 0 ? 6 (a0) (c) (c) (a7) 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 124 of 132 ? philips electronics n.v. 2005 rr a function: rotate accumulator right description: the eight bits in the accumulator are rotated one bi t to the right. bit 0 is ro tated into the bit 7 posi- tion. no flags are affected. example: the accumulator holds the value 0c5h (11000101b). the instruction, rr a leaves the accumulator holding the value 0e2h (11100010b) with the carry unaffected. bytes: 1 cycles: 1 encoding: operation: rr (a n ) (a n+1 ), n = 0 ? 6 (a7) (a0) rrc a function: rotate accumulator right through the carry flag description: the eight bits in the accumulator and the carry fl ag are together rotated one bit to the right. bit 0 moves into the carry flag; the original state of the carry flag moves into the bit 7 position. no other flags are affected. example: the accumulator holds the value 0c5h (1100010 1b), and the carry is zero. the instruction, rrc a leaves the accumulator holding the value 62 (01100010b) with the carry set. bytes: 1 cycles: 1 encoding: operation: rrc (a n ) (a n+1 ), n = 0 ? 6 (a7) (c) (c) (a0) 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 125 of 132 setb function: set bit description: setb sets the indicated bit to one. setb can oper ate on the carry flag or any directly address- able bit. no other flags are affected. example: the carry flag is cleared. output port 1 has been written with the value 34h (00110100b). the instructions, setb c setb p1.0 will leave the carry flag set to 1 and change the data output on port 1 to 35h (00110101b). setb c bytes: 1 cycles: 1 encoding: operation: setb (c) 1 setb bit bytes: 2 cycles: 1 encoding: operation: setb (bit) 1 sjmp rel function: short jump description: program control branches unconditionally to the address indicated. the branch destination is computed by adding the signed displacement in the second instruction byte to the pc, after in- crementing the pc twice. therefor e, the range of destinations allowed is from 128 bytes preced- ing this instruction to 127 bytes following it. example: the label ?reladr? is assigned to an instruction at program memory location 0123h. the in- struction, sjmp reladr will assemble into location 0100h. after the instruction is executed, the pc will contain the value 0123h. ( note: under the above conditions the instruction following sjmp will be at 102h. there- fore, the displacement byte of the instruction wi ll be the relative offset (0123h-0102h) = 21h. put another way, an sjmp with a displacement of 0feh would be a one-instruction infinite loop.) bytes: 2 cycles: 2 encoding: operation: sjmp (pc) (pc) + 2 (pc) (pc) + rel 1 1 0 1 0 0 1 1 1 1 0 1 0 0 1 0 bit address 1 0 0 0 0 0 0 0 rel. address
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 126 of 132 ? philips electronics n.v. 2005 subb a, function: subtract with borrow description: subb subtracts the indicated variable and the ca rry flag together from the accumulator, leaving the result in the accumulator. subb sets the carry (borrow) flag if a borrow is needed for bit 7, and clears c otherwise. (if c was set before executin g a subb instruction, this indicates that a borrow was needed for the previous step in a multip le precision subtraction, so the carry is sub- tracted from the accumulator along with the sour ce operand.) ac is set if a borrow is needed for bit 3, and cleared otherwise. ov is set if a borrow is needed into bit 6, but not into bit 7, or into bit 7, but not bit 6. when subtracting signed integer s ov indicates a negative number produced when a negative value is subtracted from a positive value, or a positive result when a positive number is subtracted from a negative number. the source operand allows four addressing modes: re gister, direct, register-indirect, or immediate. example: the accumulator holds 0c9h (11001001b), register 2 holds 54h (01010100b), and the carry flag is set. the instruction, subb a,r2 will leave the value 74h (01110100b) in the accumulator, with the carry flag and ac cleared but ov set. notice that 0c9h minus 54h is 75h. the difference between this and the above result is due to the carry (borrow) flag being set before the operation. if the state of the carry is not known before starting a single or multiple-precision subtract ion, it should be explicitly cleared by a clr c instruction. subb a,rn bytes: 1 cycles: 1 encoding: operation: subb (a) (a) ? (c) ? (r n ) subb a,direct bytes: 2 cycles: 1 encoding: operation: subb (a) (a) ? (c) ? (direct) subb a,@ri bytes: 1 cycles: 1 encoding: operation: subb (a) (a) ? (c) ? (r i ) subb a,#data bytes: 2 cycles: 1 encoding: operation: subb (a) (a) ? (c) ? (#data) 1 0 0 1 1 r r r 1 0 0 1 0 1 0 1 direct address 1 0 0 1 0 1 1 i 1 0 0 1 0 1 0 0 immediate data
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 127 of 132 swap a function: swap nibbles within the accumulator description: swap a interchanges the low- and high-order nibbles (four-bit fields) of the accumulator (bits 3-0 and bits 7-4). the operation can also be thought of as a four-bit rotate instruction. no flags are af- fected. example: the accumulator holds the value 0c5h (11000101b). the instruction, swap a leaves the accumulator holding the value 5ch (01011100b). bytes: 1 cycles: 1 encoding: operation: swap (a 3-0 ) ? (a 7-4 ) xch a, function: exchange accumulator wi th byte variable description: xch loads the accumulator with the contents of t he indicated variable, at the same time writing the original accumulator contents to the indica ted variable. the source/destination operand can use register, direct, or register-indirect addressing. example: r0 contains the address 20h. the accumulator holds the value 3fh (00111111b). internal ram location 20h holds the value 75h (01110101b). the instruction, xch a,@r0 will leave the ram location 20h holding the values 3fh (00111111b) and 75h (01110101b) in the accumulator. xch a,rn bytes: 1 cycles: 1 encoding: operation: xch (a) ? (r n ) xch a,direct bytes: 2 cycles: 1 encoding: operation: xch (a) ? (direct) xch a,@ri bytes: 1 cycles: 1 encoding: operation: xch (a) ? ((r i )) 1 1 0 0 0 1 0 0 1 1 0 0 1 r r r 1 1 0 0 0 1 0 1 direct address 1 1 0 0 0 1 1 i
handshake solutions HT80C51 user manual 80c51 family instruction set ? instruction definitions page 128 of 132 ? philips electronics n.v. 2005 xchd a,@ri function: exchange digit description: xchd exchanges the low-order nibble of the accu mulator (bits 3-0), generally representing a hexadecimal or bcd digit, with that of the intern al ram location indirectly addressed by the speci- fied register. the high-order nibbles (bits 7-4) of each register are not affected. no flags are af- fected. example: r0 contains the address 20h. the accumulator holds the value 36h (00110110b). internal ram location 20h holds the value 75h (01110101b). the instruction, xchd a,@r0 will leave ram location 20h holding the value 76h (01110110b) and 35h (00110101b) in the ac- cumulator. bytes: 1 cycles: 1 encoding: operation: xchd (a 3-0 ) ? ((ri 3-0 )) xrl , function: logical exclusive-or for byte variables description: xrl performs the bitwise logical exclusive-or operation between the indicated variables, storing the results in the destination. no flags are affected. the two operands allow six addressing mode comb inations. when the desti nation is the accumu- lator, the source can use register, direct, regist er-indirect, or immediate addressing; when the des- tination is a direct address, the source ca n be the accumulator or immediate data. ( note: when this instruction is used to modify an output port, the value used as the original port data will be read from the output dat a latch, not the input pins.) example: if the accumulator holds 0c3h (11000011b) and register 0 holds 0aah (10101010b) then the instruction, xrl a,r0 will leave the accumulator holding the value 69h (01101001b). when the destination is a directly addressed byte, this instruction can complement combinations of bits in any ram location or hardware register. the pattern of bits to be complemented is then determined by a mask byte, either a constant cont ained in the instruction or a variable computed in the accumulator at run-time. the instruction, xrl p1,#00110001b will complement bits 5, 4, and 0 of output port 1. 1 1 0 1 0 1 1 i
HT80C51 user manual 80c51 family instruction set ? instruction definitions handshake solutions ? philips electronics n.v. 2005 page 129 of 132 xrl a,rn bytes: 1 cycles: 1 encoding: operation: xrl (a) (a) (r n ) xrl a,direct bytes: 2 cycles: 1 encoding: operation: xrl (a) (a) (direct) xrl a,@ri bytes: 1 cycles: 1 encoding: operation: xrl (a) (a) (r i ) xrl a,#data bytes: 2 cycles: 1 encoding: operation: xrl (a) (a) #data xrl direct,a bytes: 2 cycles: 1 encoding: operation: xrl (direct) (direct) (a) xrl direct,#data bytes: 3 cycles: 2 encoding: operation: xrl (direct) (direct) #data 0 1 1 0 1 r r r 0 1 1 0 0 1 0 1 direct address 0 1 1 0 0 1 1 i 0 1 1 0 0 1 0 0 immediate data 0 1 1 0 0 0 1 0 direct address 0 1 1 0 0 0 1 1 direct address immediate data
handshake solutions HT80C51 user manual list of tables page 130 of 132 ? philips electronics n.v. 2005 appendix a1: list of tables [table 1] 80c51 sfr rese t values................................................................................................. 18 [table 2] interrupt signals, vector s and priori ties. .......................................................................... 23 [table 3] timer 0 as a timer ............................................................................................................ 3 1 [table 4] timer 0 as a counte r ........................................................................................................ 31 [table 5] timer 1 as a timer ............................................................................................................ 3 2 [table 6] timer 1 as a counte r ........................................................................................................ 32 [table 7] timer 1 generated commonl y used baud rates ............................................................ 36 [table 8] serial port setup.............................................................................................................. .40 [table 9] serial clock rate s (needs update) ................................................................................... 57 [table 10] master transmitter mode (not ava ilable for slave- only version)....................................... 65 [table 11] master receiver mode (not avail able for slave-on ly version)........................................... 66 [table 12] slave receiv er mode........................................................................................................ 68 [table 13] slave transmi tter m ode.................................................................................................... 69 [table 14] miscellaneou s states ........................................................................................................ 70
HT80C51 user manual list of figures handshake solutions ? philips electronics n.v. 2005 page 131 of 132 a2: list of figures [figure 1] HT80C51 architecture (cpu centered) .............................................................................. 7 [figure 2] HT80C51 achi tecture.......................................................................................................... 8 [figure 3] HT80C51 memo ry map....................................................................................................... 9 [figure 4] memory map of in ternal data ........................................................................................... 10 [figure 5] lower 128 bytes of ram, dire ct and indirect addressing ................................................. 11 [figure 6] sfr memory map ............................................................................................................. 13 [figure 7] interrupt response timing diagram ................................................................................. 24 [figure 8] interrupt sources from the timers 0 and 1 ...................................................................... 28 [figure 9] timer/counter mode 0: 13bit counter ............................................................................... 29 [figure 10] timer/counter mode 2: 8bit auto-re load. ....................................................................... 30 [figure 11] timer/counter 0 mode 3: two 8bit c ounters. ................................................................. 30 [figure 12] block diagram of serial interface in mode 0 ................................................................. 37 [figure 13] block diagram of serial inte rface in mode 1, 2, and 3 .................................................. 39 [figure 14] typical i 2 c bus config uration........................................................................................ 48 [figure 15] data transfer on the i 2 c bus ........................................................................................ 48 [figure 16] i 2 c bus serial interfac e block di agram......................................................................... 50 [figure 17] arbitration pr ocedure..................................................................................................... 51 [figure 18] serial clock sy nchronization......................................................................................... 52 [figure 19] serial input/output configurat ion .................................................................................. 54 [figure 20] shift-in and shi ft-out timing .......................................................................................... 55 [figure 21] format and states in the master transm itter m ode...................................................... 61 [figure 22] format and states in the master receiv er mode.......................................................... 62 [figure 23] format and states in t he slave receiv er m ode............................................................ 63 [figure 24] format and states of the slave transmit ter mode........................................................ 64 [figure 25] simultaneous repeated start c onditions from 2 masters ........................................ 71 [figure 26] forced access to a busy i2c bus ................................................................................. 72 [figure 27] recovering from a bus obstruction caused by a low level on sda .......................... 73 [figure 28] spi block di agram ......................................................................................................... 77 [figure 29] data clock timi ng diagram........................................................................................... 78 [figure 30] spi single master single slave config uration .............................................................. 79 [figure 31] functional diagram of t he t3 watchdog timer............................................................. 81
handshake solutions HT80C51 user manual document history page 132 of 132 ? philips electronics n.v. 2005 a3: document history date author version-no change report 17.3.2005 uk 1.1 first draft 22.3.2005 uk 1.1.1 ht80c 51 block diagram added. initialization chapters for interr upt controller, timers 0/1 and uart added. pins extint0_n and extint1_n used as external interupt inputs for the timers 0/1. clock input for timers and serial interfaces is the core clock (pin cclk), now. sfr xramp added. description of i 2 c interface added. 12.4.2005 uk 1.3 name s of pins adapted. description of spi and des added. block diagrams of HT80C51 changed. chapter about clocks added. sfr map updated. reset values updated. option names added. description of sio condensed. 25.4.2005 uk 1.4 mi nor changes in description of sio. description of dkey fo r the des changed. 25.4.2005 uk 1.5 some typos removed. 30.05.2005 cv, uk 1.6 update of illustrat ions (ch. 1-5.4 and 5.8-end) and formats. description of des updated and extended. 27.6.2005 cv 1.7 update of ill ustrations (ch. 5.5, 5.6). update of figure 6 and table 7.

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